JPS58151188A - Digital multi-frequency receiver - Google Patents

Abstract

PURPOSE:To prevent malfunction due to noise, by outputting a multi-frequency signal when the rate of change in power of an input signal is a prescribed value or below or when the multi-frequency code is changed. CONSTITUTION:A majolity logic circuit 16 outputs an SP signal to a terminal 14 when either or a code change detection signal (h) or a power attenuation detection signal (m) is inputted at least to an effective signal (e) inputted from a code check circuit 11, and the circuit 16 inputs a hold signal (f) to a code output circuit 13. The circuit 13 outputs a multi-frequency code (g) to a terminal 15 and holds the same frequency code (g) while the signal (f) is received. When an impulsive noise is inputted from a terminal 0, the rate of change in power (k) is larger than the threshold value 1, and the signal (m) is not inputted to the circuit 16. Thus, even if two effective frequencies are eventually detected on the way, no SP signal is outputted from the terminal 14.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a digital multi-frequency receiver, in particular, to a digital multi-frequency receiver that receives a time-division multiplexed digital multi-frequency signal and converts the component frequencies of the input signal using discrete Fourier transform. The present invention relates to a digital multifrequency receiver that extracts and identifies predetermined multifrequency symbols.

lb) Background of the Technology In telephone exchange networks, a multi-frequency signaling system that transmits a selection signal or a monitoring signal by a combination of frequencies selected from a plurality of predetermined frequencies within the voice band is known as a push-button dialing signaling system ( PB multiplexed signals or multifrequency signaling systems (MF multiplexed signals) in inter-office trunk lines are widely adopted.On the other hand, communication channel power of telephone exchanges, etc.; Digital techniques such as discrete Fourier transform are also widely used in receiving means.

(C1 Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional digital multifrequency receiver used for receiving the MF multiplied signal.
As is known in the art, a predetermined selection signal is constructed by a combination of two frequencies (hereinafter referred to as a multifrequency code) among six signal frequencies ranging from 700 to 17oO Hertz.

In FIG. 1, the digital multi-frequency receiver is composed of a discrete Fourier transform calculation section A, a signal detection section B, and a signal determination section C. Input signal a that is input from terminal 0 and is digitally encoded and compressed by a predetermined companding side.
The sample values of are converted into linear codes by the expander l of the discrete Fourier transform calculation unit A, and after being standardized, are input to the multipliers 12 and 2', and the six signal frequencies are converted to the reference angle. The kernel cos(ωnT) with frequency ω and s i
n (ωnT) (where T is the sampling period of input signal a, n
is the sample value number) is multiplied in a time-sharing manner, and then input to two multipliers 112 and 2', respectively, and is input to the predetermined integration interval NT (where N is the total number of samples in the integration interval, so n −0
N-1), multipliers 4 and 4'
Also, via the adder 5, the electric scum vector b at each of the signal frequencies is calculated and output to the terminal 6. The electric waste vector b is input to the threshold circuit 7 and the delay circuit 8 of the signal detection section B. The threshold circuit 7 is connected to each integral interval NT.
At each time, the maximum value is selected from among the electric scum vectors b for the six input signal frequencies, and a value that is a predetermined level lower than the maximum value is determined as the threshold value C, and is input to the comparison circuit 9. On the other hand, the delay circuit 8 gives the inputted electric scum vector b a delay time comparable to when the threshold value circuit 7 outputs the threshold value C, and then inputs it to the comparison circuit 9 . The comparator circuit 9 calculates the electric current vector b corresponding to each signal frequency input from the delay circuit 8.
is compared with a threshold value C input from the threshold value circuit 7, and a signal frequency having an electric scum vector b greater than or equal to the threshold value C is regarded as an effective frequency, and other signal frequencies are regarded as invalid frequencies. A frequency detection signal d having a logical value of 0 is outputted to the terminal 10 in response to the logical value l and the invalid frequency. The frequency detection signal d is input to the code checking circuit 11 and the code output circuit 13 of the signal determining section C. Code check circuit 11
checks the number of effective frequencies by adding the logical values of the frequency detection signal d input for each integral interval NT,
Multi-frequency code g that is valid only when the number of effective frequencies is 2
is assumed to have been detected, and inputs the valid signal e to the majority logic circuit 12. The majority logic circuit 12 performs a majority decision on the valid signal e inputted from the code checking circuit 11 over several integration intervals NT to prevent momentary interruption, and then outputs a valid multi-frequency code g to the terminal 14. It outputs an SP flaw signal indicating that it is receiving, and also inputs a holding signal f to the code output circuit 13. The code output circuit 13 outputs the frequency detection signal d input from the terminal 10 as a multi-frequency code g to the terminal 15, but the holding signal f is output from the majority logic circuit 12.
While receiving, the multi-frequency code g to be output is held, and even if the input frequency detection signal d changes during the reception, the multi-frequency code g to be output does not change.

As is clear from the above explanation, in a conventional digital multi-frequency receiver, the signal determining section C is provided with instantaneous interruption prevention, so the multi-frequency code g output from the terminal 15 is
It is held while the P signal is being sent.

Therefore, for example, if the input signal a includes an impulsive noise that occurs at time to and gradually attenuates as shown in FIG. Misidentified as frequency code g and SP damage signal time t1
When output thereafter, the erroneously recognized multi-frequency code g is continuously output from the terminal 15. Therefore, even if the true MP signal is input after time t2, the SP defect signal is still output from the terminal 14, and the misidentified multifrequency code g is still output from the terminal 15, and the multifrequency code corresponding to the true MF multiplied signal is still output. The output of g is blocked.

(dl) OBJECTS OF THE INVENTION An object of the present invention is to eliminate the drawbacks of conventional digital multi-frequency receivers as described above and to realize a digital multi-frequency receiver that can prevent malfunctions due to this type of noise.

(8) Structure of the Invention The purpose of this invention is to input a time-division multiplexed digital multi-frequency signal, extract the component frequencies of the human signal using discrete Fourier transform, and identify a predetermined multi-frequency code. In the frequency receiver, a means for detecting that a power change rate of the input signal is below a predetermined threshold value and outputting a power attenuation detection signal, and a means for detecting a change in the multifrequency code and outputting a sign change detection signal. This is achieved by providing means for outputting the multi-frequency code when at least one of the power attenuation comparison signal and the code change detection signal is detected.

(f) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing a digital multi-frequency receiver according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. The digital multi-frequency receiver shown in FIG. 3 includes a discrete Fourier transform calculation section A' and a signal detection section B1.
It consists of a signal judgment section C' and a power attenuation detection section. Since the signal detection section B is the same as that shown in FIG. 1, details are omitted. Discrete Fourier transform calculation unit A
' is the sample value of input signal a input from terminal O, which is expanded by 4.
! After linear encoding and scaling by 11, the kernels cos(ωnT) and 5in(ωnT) are time-divisionally multiplied by a constant 1 by two multipliers 2 and 2',
The integrators 3 and 3', the multipliers 4 and 4', and the adder 5 divide the power for the same six signal frequencies as in FIG. The electric waste vector b is input to the signal detection section B, and a frequency detection signal d is outputted to the terminal 10 for each integral interval NT through a process similar to that shown in FIG. The frequency detection signal d is input to the code check circuit 11, code output circuit 13, delay circuit 21, and comparison circuit 22 of the signal determination section C. The code checking circuit 11 checks the validity of the frequency detection signal d as a multi-frequency code g by a process similar to that shown in FIG. 1, and inputs a valid signal e to the majority logic circuit 16 based on the result.

Further, the delay circuit 21 receives the input frequency detection signal d.
After being delayed by the integration interval NT, the signal is transmitted to the comparator circuit 22. The comparison circuit 22 converts the frequency detection signal d directly input from the terminal 10 into one integral period N transmitted from the delay circuit 21.
It is compared with the frequency detection signal d before T, and if a change is detected, the sign change detection signal d is inputted to the majority logic circuit 16. On the other hand, the total power b' output from the discrete Fourier transform calculation unit A' to the terminal 6 is input to the power attenuation detection unit,
A power change rate k in one integration interval NT is determined by a delay circuit 17 having a delay time of one integration interval NT and a subtraction circuit 18 and is inputted to a comparison side 19. Comparison circuit 19
is the input power change rate k as a predetermined threshold value! When it is determined that the power is less than the threshold l, the power attenuation detection signal m is outputted to the terminal. The power attenuation detection signal m is sent to the signal determination section C'
is inputted to the majority logic circuit 16 of. Majority logic side 16
is the same as the majority logic circuit 12 in FIG. After processing, the SP signal is output to the terminal 14 and the holding signal f is input to the code output circuit 13. The code output circuit 13 outputs the multi-frequency code g to the terminal 15 in the same manner as in FIG. 1, and holds the same multi-frequency code g while receiving the holding signal f. When a human input signal a as shown in FIG. 2 is input to the digital multi-frequency receiver from terminal 0, a time t occurs.

Since the period from t2 to t2 is shocking noise, the total power b' changes rapidly, and the power change rate is larger than the threshold l, so the power attenuation detection signal m is not input to the majority logic circuit 16. Therefore, even if even two effective frequencies are detected on the way, the SP signal will not be output from the terminal 14. Time t2pt
Since the true MF multiplied signal is input when the power decreases, the total power b' is stable and the power change rate is less than the threshold l, so the power attenuation detection signal m is input to the majority logic circuit 16 and the terminal 14 is The SP signal and the multifrequency code g corresponding to the MF multiplied signal are output to the terminal 15. Note that before the power change rate k becomes equal to or less than the threshold value l, the comparator circuit 22 detects a change from the frequency detection signal d caused by noise to the frequency detection signal d caused by the true MF multiplied signal, and detects a sign change. Upon outputting the signal e, the majority logic circuit 16 starts processing the valid signal e from that point. Note that when only the true MF multiplied signal is input as the input signal a, the power attenuation detection signal m is output from the power attenuation detection section from the beginning, so the majority logic circuit 16 immediately processes the valid signal e. Start.

As is clear from the above description, according to this embodiment, SP
The signal is output from terminal 1 unless at least one of the power attenuation detection signal m and the power change rate is input to the majority logic circuit 16.
Since the digital multi-frequency receiver is not outputted to the digital multi-frequency receiver 4, malfunctions of the digital multi-frequency receiver are prevented.

Note that FIG. 3 is merely one embodiment of the present invention, and the configurations of the signal determination section C' and the power attenuation detection section, for example, are not limited to those shown in the figure, and may be modified in many other ways. However, the effects of the present invention do not change in either case. It goes without saying that the object of the present invention is not limited to the digital multi-frequency receiver that receives the MF multiplied signal.

(g) Effects of the Invention As described above, according to the present invention, it is possible to realize a digital multi-frequency receiver that can prevent malfunctions caused by noise.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional digital multi-frequency receiver, FIG. 2 is a diagram showing an example of an input signal waveform including noise and an MF multiplied signal, and FIG. 3 is a diagram showing an example of a digital multi-frequency receiver according to an embodiment of the present invention. FIG. 3 is a diagram showing a frequency receiver. In the figure, A and A' are discrete Fourier transform calculation units, B is a signal detection unit, C and C' are signal determination units, D is a power attenuation detection unit, ■ is an expander, 2.2', 4 and 4 ' is a multiplier, 3 and 3' are integrators, 5 is an adder, 7 is a threshold circuit, 8.17 and 21 are delay circuits, 9.19 and 22 are comparison circuits, 11 is a code check circuit, 12 and 16
is the majority logic circuit, 13 is the sign output circuit, 18 is the subtraction circuit, 0.6, l0114.15 and addition are the terminals, a is the input signal, b is the electric waste vector, b' is the total 7 power, C and I are threshold, d is the frequency detection signal, e is the effective signal, f is the holding signal, g is the multifrequency code, h is the sign change detection signal, k
is the power change rate, m is the power attenuation detection signal, and t□, tl and t2 are the time points.

Claims (1)

[Claims] A digital multifrequency receiver inputs a time division multiplexed digital multifrequency signal, extracts the component frequency of input No. 1 using discrete Fourier transform, and identifies a predetermined multifrequency code. means for detecting that the rate of change in power is below a predetermined threshold and outputting a power attenuation detection signal; and means for detecting a change in the multi-frequency code and outputting a sign change detection signal; A digital multi-frequency receiver, characterized in that it outputs the multi-frequency code when detecting either a small signal or a code change detection signal.