JPS6347184B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal determination circuit for a digital multifrequency signal receiver, and more particularly, to a signal determination circuit for a digital multifrequency signal receiver that determines the validity of a received digital multifrequency signal.

Generally, in a digital multi-frequency signal receiver, the presence or absence of a received signal is detected by comparing the received digital multi-frequency signal with a certain threshold value, and furthermore, the validity of the received signal is determined. To determine the validity of this received signal, for example, for a multi-frequency signal (MF signal), since the MF signal consists of a combination of two of six frequencies, it is detected whether two of the six frequencies are present. 2/6 check is performed and push button signal (PB signal)
Since the PB signal consists of a combination of 4 frequencies in the high group and 4 frequencies in the low group, with 1 frequency in each group, it is necessary to detect whether or not there is one frequency among the 4 frequencies in the high group, and 4 frequencies in the low group. A 1/4 and 1/4 check is performed to detect whether one of the frequencies exists.

FIG. 1 shows a block system diagram of an example of a signal determination circuit of a conventional digital multi-frequency signal receiver. In the figure, a digital multi-frequency detection signal received by a digital multi-frequency signal receiver enters input terminal 1 as a serial data flow, and this detection signal is serial-parallel converted by a serial-parallel converter 2 and then read.・
It is supplied to only memory (ROM) 3.
Correct data is stored in the ROM 3, which is compared with the output parallel signal of the serial-to-parallel converter 2, and sent from the output terminal 4 through a majority logic circuit (not shown) to generate a determination signal as to whether or not the received signal is valid. is output. However, this conventional circuit has the drawbacks of high cost and high power consumption.

Other conventional signal determination circuits have used gate circuits, but these have the disadvantage of complicating the circuit configuration.

An object of the present invention is to provide an inexpensive and versatile digital multifrequency signal receiver with a simple circuit configuration by sequentially adding the output detection signals of a detection circuit that detects the presence or absence of a received digital multifrequency signal. The present invention provides a signal determination circuit.

The present invention provides a detection circuit that detects the presence or absence of reception for each of the plurality of frequencies from a received signal of a digital multifrequency signal in which a certain number of frequencies among the plurality of frequencies are multiplexed and the combination of the multiplexed frequencies represents predetermined information. an adder that is provided at the output stage of the detection circuit and sequentially adds the output detection signals of the detection circuit;
A logic circuit detects whether the number of received frequencies is the above-mentioned fixed number from the output signal of the adder, and the logic circuit outputs a judgment signal for determining the validity of the received signal, thereby solving the above-mentioned drawbacks. An embodiment thereof will be described below with reference to FIGS. 2 and 3.

FIG. 2 shows a block system diagram of a PB signal receiver to which an embodiment of the signal determination circuit of the digital multi-frequency signal receiver according to the present invention is applied. In the figure, 5 is an input terminal, into which a PB signal from a push-button dial telephone (not shown) is input. As is well known, as shown in Figure 3, this PB signal is 1209Hz, 1336Hz,
One of the four high group frequencies of 1477Hz and 1633Hz
frequency and one frequency out of the four low group frequencies of 697Hz, 770Hz, 852Hz and 941Hz are assigned to each button, and by pressing a button, one of the low group frequencies assigned to that button is assigned. 1
It is a signal in which a frequency and one frequency among high group frequencies are multiplexed, and pulse code modulation (PCM) is used.
This is an 8-bit PCM signal. In addition, the third
As shown in the figure, 1633Hz is not currently used.

This PB signal is supplied in series from input terminal 5 to expander circuit 6, where it is linearly encoded.
After the signal is converted into a 16-bit PCM signal, it is supplied to band elimination filters 7 and 8, which are digital filters, respectively. The high group frequency is removed by the band elimination filter 7 and the low group frequency is taken out, and the limiter 9
The signals are converted into rectangular waves using a predetermined threshold value and then supplied to band filters 11, 12, 13 and 14, respectively. On the other hand, the band elimination filter 8 removes the low frequency group and extracts the high group frequency, which is converted into a rectangular wave by a limiter 10 at a predetermined threshold value and then supplied to the band filters 15, 16, 17 and 18, respectively. The bandpass filters 11 to 18 each select and output a signal of a predetermined frequency by discrete Fourier transform (DFT). Here, the passbands of bandpass filters 11, 12, 13, and 14 are set to 697Hz, 770Hz, 852Hz, and 941Hz, respectively, and the passbands of bandpass filters 15, 16, 17, and 18 are set to 1209Hz, 1336Hz, and 1336Hz, respectively. 1477Hz
and 1633Hz, and the band filter 11
.about.18 output signals are supplied to a detection circuit 19, respectively.

The detection circuit 19 includes the band filters 11 to 18 described above.
It is detected from the output signal whether or not a total of 8 frequencies, 4 frequencies in the high group and 4 frequencies in the low group, have been received, and a total of 8 bits of detection signal corresponding to each frequency is outputted in time series. This detection signal is supplied to the memory circuit 20 and stored there, and is also supplied to the adder 22 in the signal determination circuit 21 which represents one embodiment of the present invention. Since the output signal of the adder 22 is temporarily stored in the latch circuit 23 and then supplied to the adder 22, the adder 22 sequentially adds each bit output of the detection signal. Detection signal is top 4
For example, the bits indicate the presence or absence of receiving inputs for each of the four high group frequencies, and the lower four bits indicate the presence or absence of receiving inputs for each of the four low group frequencies, and when the value of a bit is logic "1", that bit is , the addition output signal of the adder 22 is passed through the latch circuit 23 and held in the latch circuit 24 at the time when the upper four bits of the detection signal are added. Similarly, adder 2
2, when the lower four bits of the detection signal are added, the addition output signal is held in the latch circuit 25 via the latch circuit 23.

The output signals of the latch circuits 24 and 25 are supplied to a gate circuit 28 via gate circuits 26 and 27 which are in an "open" state when the signal is "1". Therefore, the latch circuit 24 and the gate circuit 26 reduce the frequency to 1/4 of the high group frequency.
A check is performed, and the latch circuit 25 and gate circuit 27 perform a 1/4 check of the low group frequency. The gate circuits 26 and 27 have four gate circuits each for the high group and the low group.
The gate circuit 28 is configured to output a logic "1" signal when only one of the frequencies is received, and to output a logic "0" signal otherwise. Outputs a logic “1” signal only when both input signals are logic “1”,
At other times, it is configured to output a logic "0" signal. Therefore, the gate circuit 28 performs a 1/4 and 1/4 check.

The output signal of the gate circuit 28 is sent to the majority logic circuit 2.
9. The majority logic circuit 29 generates a determination signal for determining the validity of the received signal, that is, a signal present signal ( SP signal) is generated and output to the output terminal 31, while also being supplied to the memory circuit 20, so that even if there is a momentary interruption or the like in the received PB signal, the stored data is retained. The data stored in the memory circuit 20 is output from the output terminal 30, and the data stored in the memory circuit 20 is output from the output terminal 31.
It is supplied to a central processing unit (not shown) together with the SP signal extracted from the .

Therefore, for example, □5 of a push button dial telephone
When the button is pressed, a multiplexed signal of 770 Hz and 1336 Hz is received, and the signals are extracted from the band filters 12 and 16 and supplied to the detection circuit 19. The output signal of the detection circuit 19 is, for example, the third bit of the upper four bits and the third bit of the lower four bits.
Each bit is a logic "1" and the other bits are a logic "0" signal, which are supplied to the memory circuit 20 and the signal determination circuit 21, respectively. Signal judgment circuit 21
Perform the 1/4 and 1/4 check as described above,
In this case, the SP signal is output from the output terminal 31.

However, if the received PB signal contains a frequency component of any of the other six frequencies other than 770Hz and 1336Hz, for example, other high group frequencies due to a pseudo signal such as voice or noise, even though the □5 button is pressed. is included, the addition output signal of the upper 4 bits of the output detection signal of the detection circuit 19 becomes "2" or more, so the gate circuit 26 does not open, and therefore the SP signal is output from the majority logic circuit 29. Not done. Also PB
If the signal duration time of the signal is short, the majority logic circuit 29 repeats the signal a predetermined number of times and the gate circuit 2
Since the output signal of 8 cannot be counted, the output terminal 31
SP signal is not output. Furthermore, even if the received digital signal has a single frequency, the gate circuit 2
6 or 27 is not opened, and the SP signal is not taken out from the output terminal 31.

Note that the present invention is applicable not only to the above-mentioned PB signal receiver but also to other digital multifrequency signal receivers such as an MF signal receiver.

As described above, according to the present invention, the logic of an adder that sequentially adds detection signals, a latch circuit, a gate circuit, etc. that detects whether the number of received frequencies is a predetermined constant number from the output signal of the adder Because it consists of multiple circuits, it can be constructed at a lower cost than a conventional signal determination circuit using ROM, and the circuit configuration can be simpler than a conventional signal determination circuit consisting of a group of gate circuits. You can easily perform 3/6 checks, etc., increasing versatility.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing an example of a signal judgment circuit of a conventional digital multi-frequency signal receiver;
The figure is a block system diagram of a PB signal receiver to which an embodiment of the signal determination circuit of the digital multi-frequency signal receiver according to the present invention is applied, and FIG. 3 is a diagram for explaining general PB signal constituent frequencies. 4, 31...judgment signal (SP signal) output terminal,
5... Reception PB signal input terminal, 11-18... Band filter, 19... Detection circuit, 20... Memory circuit, 21... Signal judgment circuit, 22... Adder,
23-25...Latch circuit, 26-28...Gate circuit, 29...Majority logic circuit.

Claims (1)

[Claims] 1 Output of a detection circuit that detects the presence or absence of reception for each of the plurality of frequencies from a received signal of a digital multi-frequency signal in which a certain number of frequencies among the plurality of frequencies are multiplexed and the combination of the multiplexed frequencies represents predetermined information. and a logic circuit that detects from the output signal of the adder whether the number of received frequencies is the predetermined number, A signal determination circuit for a digital multi-frequency signal receiver, characterized in that the logic circuit is configured to output a determination signal for determining the validity of a received signal.