JPS58151024A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58151024A JPS58151024A JP3273882A JP3273882A JPS58151024A JP S58151024 A JPS58151024 A JP S58151024A JP 3273882 A JP3273882 A JP 3273882A JP 3273882 A JP3273882 A JP 3273882A JP S58151024 A JPS58151024 A JP S58151024A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- mask
- resist
- dielectric film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 21
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- 229910052786 argon Inorganic materials 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 4
- 238000011161 development Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- -1 arsenic ions Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 101100125381 Arabidopsis thaliana IAN4 gene Proteins 0.000 description 1
- 101100014646 Mus musculus Gimap3 gene Proteins 0.000 description 1
- 101100014652 Rattus norvegicus Gimap5 gene Proteins 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、写真蝕刻法による工１！を改嵐した半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a process using a photolithography method. The present invention relates to a method of manufacturing a semiconductor device that is an improved method of manufacturing a semiconductor device.
最近、半導体装置においては高集積化が進み、ａｍ加工
技術が要求されるにつれ、写真蝕刻法による工程Ｏ作業
が非常に困難になっている。Recently, semiconductor devices have become highly integrated, and as AM processing technology is required, process O operations using photolithography have become extremely difficult.
即ち、半導体基板上の段差ノ４メーン上に７オトレノス
ト属を塗布した彼、露光、現像を行ってレジストノ臂メ
ーンを形成する際、前記段差パターンは、レジスト／母
メーンが微細にかつ複雑になる＃１ど写真蝕刻法による
工程に悪影Ｗｔ及はしている。That is, when a resist layer is formed by applying 7 otorenost on the four main steps on a semiconductor substrate, exposing and developing the step pattern, the resist/main main becomes fine and complicated. #1 The photo-etching process has negative effects.
ところで、半導体装置の製造において配線を与真蝕刻法
を用いて形成するには、従来第１図（ａ）〜（→に示す
知音方法が採用されている。まず、例え＊ｐｍ＋導体基
導体基板図上しない多結晶シリコン層を堆積しえ彼、）
譬ター二ンダしてシリコンΔメーン１を形威し、更に全
ＴＩＭＫＣｖＤ酸化膜１を堆積する（菖１ｇ１１（ａ）
図示）、つづいて、この（至）酸化層１上に配線材料と
してのムｔ−ｇｔ膜４を蒸着する（菖１１１１伽）図示
）０次に、全面に４ジ形の７オトレジス）ＩＩＪｔｌｌ
ｋ布し、この７オトレゾスト換５上に配−形成予定部に
対応する部分にマスクツ臂ｌ−ンが形成された配線用マ
スク−をセットする６次いで、この配線用マスク６を用
いて露光を行喰う（第１！！ｃｌ（＠）図示）。By the way, in the manufacture of semiconductor devices, in order to form wiring using the die etching method, the method shown in FIGS. 1(a) to (→) has conventionally been adopted. Figure 1: Depositing a layer of polycrystalline silicon (not on the diagram)
The silicon Δ main 1 is shaped by analogy, and the entire TIMKCvD oxide film 1 is further deposited (Iris 1g11(a)
(Illustrated) Next, on this oxide layer 1, a Mut-gt film 4 as a wiring material is deposited (Iris 1111).
7) Set a wiring mask on which a mask arm is formed in a portion corresponding to the area to be formed on the wiring layer 5. 6. Next, use this wiring mask 6 to perform exposure. Go eat (1st!! cl (@) illustrated).
ひきつづき、前記配線用マスク−を城〕除き、現像処ｍ
を施してレジストΔＪ−ン（図示せず）を形成する。こ
の後、このレジスト−ターンをマスクとして前記ムｔ−
ａｌｌ＠４を工、チンダ除去してムｔ −８１からなる
配＠ｒを形威し、前記レゾスト・譬ターンを除去する（
第１図＠）図示）。Continuing, remove the wiring mask and develop it.
A resist ΔJ-n (not shown) is formed by applying the following steps. After that, using this resist turn as a mask,
Edit all @4, remove Chinda, form a layout @r consisting of Mut -81, and remove the Resist/Mataan (
Figure 1 @) As shown).
しかしながら、前述し九配線の形成方法においては、露
光時、ムｔ−５ｔｊ［４が反射性を有するために、その
段差部に７オトレジスト膜５を通過して入射した光の一
部が、斜め方向に反射して配線形成予定部に対応するフ
ォトレジスト＠Ｊｏｎｓｅ露光する。その結果、現像処
理後得られるレジスト／４ターンは、当初予定した形状
よυ細まったシ、あるいは特に段差部において消滅して
残らないということが生じる。したがって、こうしたレ
ジスト／４ターンをマスクとしてｕ−１１１膜４の工、
千ンダを行なうと、ムｔ −８１からなる配線１が細く
なって抵抗が高くなったｐｌあるいは段差部で断切れが
生じる欠点がＴｏりた。However, in the above-mentioned method for forming 9 interconnects, during exposure, because the mu t-5tj[4 has reflective properties, a part of the light that has passed through the 7-oto-resist film 5 and is incident on the stepped portion is obliquely reflected. The photoresist @Jonse corresponding to the area where wiring is to be formed is exposed by reflection in the direction. As a result, the resist/4 turns obtained after the development process may become narrower than the originally planned shape, or may disappear and not remain, especially at the stepped portions. Therefore, using this resist/4 turn as a mask, the U-111 film 4 is etched.
When the wiring was carried out, the wiring 1 made of Mut-81 became thinner and had a drawback that breaks occurred at the PL or stepped portions where the resistance increased.
本発明は上記事情に龜みてなされたもので、露光時金属
膜の段差部での反射を阻止し、この反射に起因する配線
の高抵抗化や断切れを防止し九半導体装置の製造方法を
提供することを目的とするものである。The present invention has been made in view of the above-mentioned circumstances, and it prevents reflection at the stepped portion of a metal film during exposure, prevents high resistance and disconnection of wiring caused by this reflection, and improves a method for manufacturing a semiconductor device. The purpose is to provide
本発明は、半導体基板上に金属層を形成し九稜、良だち
に７オＦレジスト展を塗布して露光、現像を行うのでは
なく、金属層上Ｋｌｌ電体膜を形成し、これに不活性イ
オンを注入して該誘電体膜の表面を黒色化することＫよ
って、後工程の露光に際しレジスト／４ターンを通過し
た光を前記騎電体換の表ｍＫ吸収し、配線の高抵抗化、
断切れを防止することを図りたことを骨子とする。In the present invention, instead of forming a metal layer on a semiconductor substrate, applying a 70F resist layer on the top and bottom edges, exposing and developing it, a Kll electric film is formed on the metal layer. The surface of the dielectric film is blackened by injecting inert ions into the surface of the dielectric film, so that the surface of the dielectric film is absorbed by the light that has passed through the resist/four turns during exposure in the subsequent process, and the height of the wiring is increased. resistance,
The main point is to prevent disconnection.
本発明を第２図（１）〜←）に基づいて説明する。 The present invention will be explained based on FIG. 2 (1) to ←).
〔１〕まず、ｐｉｉｉ＊導体基板１１上に厚さ−のぼり
シリコン層（図示せず）を堆積した後、写真蝕刻法によ
）・譬ターニングしてシリコン・臂ターン１２を形成し
え、つづいて、全面に厚さ３０００ＸｏＣＶＤ −１１
０，ＩｉＪ Ｊ を堆積り九（第２ 図（ａ） ＦＫＪ
示）０次いで、全面に厚さＩＪ講のムｔ−８１換１４、
厚さ２０００１の／クズ１８１．Ｎ４膜１５を順次堆積
した。この後、砒素イオンを、ドーズ量Ｉ Ｘ １Ｇ
／３２、加速電圧６０ Ｋ＠Ｖの条件下で前記グツズ
ＹむｊＮ４膜１１にイオン注入してこのａｔ、Ｎ４ｊｌ
ｌ Ｊ Ｊの表面を黒色化した（第２９伽）図示）。[1] First, a thick silicon layer (not shown) is deposited on the PIII* conductor substrate 11, and then subjected to photolithographic turning to form the silicon arm turn 12. The entire surface is coated with a thickness of 3000XoCVD-11.
0, IiJ J is deposited (Fig. 2 (a) FKJ
(shown) 0, then the thickness of the IJ coating on the entire surface is 14,
Thickness: 20,001 mm / 181 mm. N4 films 15 were sequentially deposited. After this, arsenic ions are added at a dose of I x 1G.
/32, and an acceleration voltage of 60 K@V, ions were implanted into the at, N4, film 11.
The surface of l J J was blackened (No. 29) (illustrated).
（１〕次に、全面に厚さ３０００Ｘ （２） ／ −／
形Ｏ７。(1) Next, apply a thickness of 3000X to the entire surface (2) / - /
Shape O7.
トレジスト１ｌｘｉを塗布した。つづいて、この７オト
レジス）Ｉ［１ｇ上に配線形成予定部に対応する部分に
マスクイターンが形成されたガラスマスク１ｒをセ、ト
シた０次いで、前記ガラスマスク１ｒを用いて露光を行
った（第２１％ＣＩ（ｊ）図示）、この結果、光は７オ
トレジスト換１６を通過してプラズマ８１．Ｎ４ＩＩ
Ｊ ｓの表面Ｋａ＆され、紅−８１１１１４表面から光
が反射するのを防止され友、露光後、ガラスマスク１１
を取１除き、現像処理を施してレジスト／４ターン１８
を形成した。この彼、このレジスト／＃ ／ −７１８
をマスクとしてプラズマＩＩ ｉ ｓＮ４膜１５をリア
クティブイオン工、チンダ（ＲＩＩＣ’） Ｋて工、チ
ンダ除去して８１ Ｎ膜ノ臂ターン１＃管形成した（第
４
２図（、ｉ）図示）、ひきつづき、レジストΔｌ−ン１
１を０２７．シャ等で除去稜、１１１．Ｎ４膜Δターン
ｌ＃をマスタにしてムｔ −１１膜１４をＲＩＥにて工
、チング除去し、ムｔ −ｓｉからなる配線１０を形成
し、更Ｋｌｉ、Ｎ４膜Δターン１＃をＣＤＩ ！で除去
して所望の半導体装置を製造した（＃１２図（・）図示
）。Tresist 1lxi was applied. Subsequently, a glass mask 1r in which a mask pattern was formed in a portion corresponding to a portion where wiring was to be formed was placed on this 7 Otoregis) I[1g. Next, exposure was performed using the glass mask 1r. (21st % CI (j) shown), as a result, the light passes through the 7 photoresist exchanger 16 and enters the plasma 81. N4II
After exposure, the glass mask 11
1 removed, developed and resist/4 turns 18
was formed. This guy, this resist/#/-718
Using the plasma II i sN4 film 15 as a mask, reactive ion etching was carried out, the sN4 film 15 was removed by reactive ion processing, and the tinder was removed to form an 81 N film arm turn 1 tube (as shown in Fig. 42(,i)). , followed by resist Δl-one 1
1 to 027. Edges removed by Sha et al., 111. Using the N4 film Δ turn l# as a master, the Mut-11 film 14 is etched and removed by RIE to form the wiring 10 made of Mut-si, and then the N4 film Δ turn 1# is CDI! The desired semiconductor device was manufactured by removing the wafer (as shown in Figure #12 (•)).
しかして、前述した製造方法によれば、配線材料として
のムｔ−１１１＄１４上にグツズＭ８１．／ｉ。According to the manufacturing method described above, Gutsuzu M81. /i.
膜１５を堆積した後、砒素イオンをイオン注入して該プ
ラズマ畠ＩＡＮ４膜１１の＊ｍｒを黒色、化するため、
後工程の露光に際してフ、）レジストａＩＣを通過し先
光をプラズマＩｔ、Ｎ４換１ｊの表面に吸収することが
できる。その結果、従来の如くムｔ−ｓｔｇｏ段差部で
の光反射に伴なうレジストノ豐ターンｖＪｌ＋中段差部
におけるレジスト・臂ターンの消滅を阻止し、これをマ
スクとしてムｔ−１１１換１４を遥択エツチングするこ
とによって、高抵抗化中断切れのない設計値寸法通シの
配線１−を形成できる。After depositing the film 15, arsenic ions are implanted to turn *mr of the plasma field IAN4 film 11 black.
During exposure in the post-process, the previous light can be absorbed by the surface of the plasma It, N4 exchange 1j after passing through the resist aIC. As a result, it is possible to prevent the disappearance of the resist foot turn vJl + the resist arm turn at the middle step part due to light reflection at the step part of the mu t-stgo as in the past, and to use this as a mask, it is possible to move the mu t-111 replacement 14 far away. By selectively etching, it is possible to form the wiring 1- with the design value dimensions without interruptions in increasing the resistance.
また、ＡＡ−ｇｔ腰１４０／ヤターニングに際して、ム
ｔ−８１膜１４に対して選択工、チング性が良い！！１
．Ｎ４膜ノ母メーン１９をマスクとして工、チング除去
するため、正確な／４ターニングを行なうことができる
。Also, when turning the AA-gt waist 140/ya, it has good selection and cutting properties for the Mut-81 membrane 14! ! 1
．． Since the N4 film mother main 19 is used as a mask to remove chips, accurate /4 turning can be performed.
なお、上記実施例では不活性イオンとして砒素を用いた
が、これに限らず、リンあるいはアルノンを用いてもよ
い。Although arsenic was used as the inert ion in the above embodiment, the present invention is not limited to this, and phosphorus or arunone may also be used.
また、上記実施例ではＡｔ −８１ｊｌｌ １４の７母
ターニングに際して、ａｔ、Ｎ４／４ターンをマスクと
して行ったが、これに限らず、１９１．Ｎ４ノ４メーン
の形成に用いたレジストツヤターンをマスクトシて行っ
て−よい。Further, in the above embodiment, when performing the 7th turn of At -81jll 14, at and N4/4 turns were used as masks, but the invention is not limited to this. The resist gloss turn used for forming the N4 main layer may be performed using a mask.
以上詳述した如く本発明によれば、高抵抗化中断切れを
起ζすことなく設計値寸法通りの配線が形成し得る信頼
性の高い半導体装置の製造方法を提供できるものである
。As described in detail above, according to the present invention, it is possible to provide a highly reliable method of manufacturing a semiconductor device in which wiring can be formed according to the designed dimensions without causing high resistance interruption or breakage.
第１図（、）〜（、ｉ）は、従来の半導体装置の製造方
法を工１！拳に示す断面図、第２図（畠）〜（・）は本
発明Ｓ！導体装置の製造方法を工程順に示す断面図であ
る。
１１・・・Ｐ型半導体基板、１２・・・シリコンパター
ン、Ｊ Ｊ・ＣＶＤ−ｇｓｏ、ｌｋ、 Ｊ ４−ｈｔ−
ａｔ換、１ｊ−・ｆツズマ１１１．Ｎ４簾、１ト・・７
オトレジス） １１％ ｉ ｒ・−４９スマスタ、Ｉ
ｇ−・・レジストツヤターン、１ト・・ａ ｌ 、Ｎ４
膜Ａターン、２０・・・配線。
出願入代雇人 弁履士 鉤 江 武 彦１１ＩＩ
（ａ）
（ｂ）
（Ｃ）
第１ｍ
（ｄ）
（ｂ）
（Ｃ）
第２１１！！Ｉ
（ｄ）
（ｅ）Figures 1 (,) to (,i) show the conventional method for manufacturing semiconductor devices. The cross-sectional view shown in the fist, Figure 2 (Hata) to (・) is the present invention S! FIG. 3 is a cross-sectional view showing a method for manufacturing a conductor device in order of steps. 11... P-type semiconductor substrate, 12... Silicon pattern, J J CVD-gso, lk, J 4-ht-
AT conversion, 1j-・f Tsuzuma 111. N4 blind, 1t...7
Otregis) 11% i r・-49 Smaster, I
g-...Resist gloss turn, 1t...a l, N4
Membrane A turn, 20... wiring. Application Substitute Employer Bento Attorney Takehiko Kagoe 11II (a) (b) (C) 1st m (d) (b) (C) 211th! ! I (d) (e)
Claims (1)
Ｏ金属展金属ｌｌ電体撫を形成する工程と、この誘電体
膜に不活性イオンをイオン注入する工程と、全面に７オ
トレゾスト換を塗布する工程と、露光、現俸を行ってレ
ジストノ臂メーンを形成する工程と、このレジスト／４
′メーンをマスクとして前記誘電体膜を工、チングし誘
電体膜／１メーンを形成する工程と、前記レジスト７々
ターンあるいは誘電体膜ΔＩ−ンをマスクとして前記金
属層を工、チンダする工程とを具備することを特徴とす
る半導体装置の製造方法。 ２、 金属層がＡＡ−１１農であることを特徴とする特
許請求の範囲第１項記載の半導体装置Ｃ・製造方法。 ３、 ＩＩ誘電体膜グ２ズマ８１ 、Ｎ４膜であるこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
Ｏ製造方法。 ４、 不活性イオンがリン、砒素、アルゴンのいずれか
一つであることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。[Claims] 1. A step of forming a metal layer on a semiconductor substrate, and ? :,
A process of forming an electric conductor, a process of implanting inert ions into this dielectric film, a process of applying 7 Otoresist on the entire surface, and a process of exposing and exposing the main part of the resist. and this resist/4
'A step of etching and chiding the dielectric film using the main as a mask to form a dielectric film/one main, and a step of etching and chiding the metal layer using the resist seven turns or the dielectric film ΔI-n as a mask. A method for manufacturing a semiconductor device, comprising: 2. The semiconductor device C and manufacturing method according to claim 1, wherein the metal layer is made of AA-11. 3. The method for manufacturing a semiconductor device O according to claim 1, wherein the second dielectric film is a N4 film. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the inert ion is one of phosphorus, arsenic, and argon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3273882A JPS58151024A (en) | 1982-03-02 | 1982-03-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3273882A JPS58151024A (en) | 1982-03-02 | 1982-03-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58151024A true JPS58151024A (en) | 1983-09-08 |
Family
ID=12367169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3273882A Pending JPS58151024A (en) | 1982-03-02 | 1982-03-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58151024A (en) |
-
1982
- 1982-03-02 JP JP3273882A patent/JPS58151024A/en active Pending
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