JPS58148515A - Encoder and decoder - Google Patents

Abstract

PURPOSE:To improve the accuracy of an encoder/decoder, by providing a switch between a switch side terminal of a main and a sub-C ladder and ground, and between the terminal and an output of a buffer amplifier respectively and cancelling an offset voltage stored in the sub-ladder. CONSTITUTION:A companding type decoder is constituted with a condencer ladder, one end of the main C-ladder and the sub-C-ladder of the decoder is connected in common and connected to a non-inverting input of the buffer amplifiers 207, 206. The reset switches 204, 205 are provided between one end of the main and the sub-C-ladder and ground GND, and offset correction switches 208, 209 are provided between terminals of SA1-SA8, SB1-SB4 of the main and the sub-C-ladder and the GND, and between the terminals and the output of the buffer 206 respectively. Further, the DC offset voltage stored in the sub-C-ladder is cancelled automatically, allowing to improve the accuracy of the decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoder/decoder using a capacitor ladder.

Figure 1 shows the configuration of a companding decoder using a conventional condenser ladder (hereinafter abbreviated as C ladder).

Here, we will explain the current commonly used μmI
The part of the aw15 polygonal line approximation companding decoder excluding the control system is shown. C ladder is lCA, 2CA.

It consists of a main C ladder consisting of 128CA, and a sub C ladder consisting of 2C0°4CB, . 10
It is connected to the non-inverting input side of 7,106. Main C
The other end of the rudder is each main C ladder switch SAI
, SA2. . . . It is switched and connected to the ground (hereinafter abbreviated as GND), the reference power supply, or the output of the buffer amplifier 106 via the SA8. On the other hand, the other ends of the sub-C ladders (excluding 3CB) are connected to GND or a reference power source via sub-C ladder switches SBI, SR2, . . . SB4, respectively.

3CB is connected to GND. 10 is μmlaw
8-bit P encoded according to the 15-fold line approximation companding rule
In the CM signal, B1 indicating the sign bit is the reference power supply voltage (
It controls a switch 102 that changes the polarity of the voltage (Vref or -Vtef). The remaining portions B2 to B8 of the PCM signal 101 are input to the code conversion circuit lθ3. Input P
According to the logic values of the CM signals B2 to B8, the logic values of the code conversion outputs are obtained as shown in Table 1.

Table 1 Code Conversion Table In Table 1, the symbols 1'', 0# and °゛S'' indicate that the corresponding main C ladder switches SAI to SA8 and sub C ladder switches SBI to SB4 are vr
ef, GND, and v8B (output potential of the buffer amplifier 106). The switching operation of these switches is performed by the output of the code conversion circuit 103. Reset switches 104 and 105 are provided between the common electrode and GND to discharge the charges stored in the main C ladder and the sash C ladder, respectively.

Next, the operation of the circuit shown in FIG. 1 will be explained. First, when the reset switches 104 and 105 are connected to GND, the charges in the main C ladder and sub C ladder are discharged.
”.At this time, the main C ladder switch SA
I~SA8. Sub-C ladder switches SB and 1-8B4 are each connected to GND. Next, reset switch 1
04, 105, input the PCM signal 101, and
According to l, changeover switch 102 is set to +■ref or -■. Connect to f. Similarly, B2 to B8 are input to the code conversion circuit 103, and the codes are converted according to Table 1, and each output S
Determine the states of the switches corresponding to AI-SA8, 5BI-8B4. At this time, buffer amplifier 1 of sub-C ladder
V8B when there is no DC offset in 06 is as follows. Here, SBi takes a value of 1" or 0" according to Table 1(b). Similarly, the main ladder output Vout is... (2) Here, SAk takes the value of "1" or o according to Table 1 (a). However, S is " It takes a value of 0".

According to Table 1(a), SAk' takes a value of "1" only for S and a value of "0" for all others.

Now, assuming that there is a DC offset between the sub C ladder buffer amplifier 106 and the main C ladder buffer amplifier 107, the above equation (2) becomes as follows.

10Voff2・・・・・・・・・
・・・・・・・・・(3) V here. ff1 indicates the sub-C ladder buffer amplifier offset, and voff2 indicates the main C ladder buffer amplifier offset.

Equation (3) shows that the DC offset of the main C ladder buffer amplifier 107 is the output voltage ■. utVcVo((2take directa
This means that the DC offset of the sub-C ladder buffer amplifier 106 affects the step error of the output level. Therefore, if the DC offset voltage of the sub-C ladder buffer amplifier 106 is large, the characteristics of the decoder will deteriorate.

The same can be said of the sub-C ladder of a feedback encoder having a local decoder using a C ladder.

An object of the present invention is to provide an encoder/decoder equipped with a circuit that automatically corrects the DC offset of a buffer amplifier.

In this invention, the above object is achieved by inserting a switch between the main C ladder and sub C ladder terminals on the ladder switch side and GND, and between the terminals on the ladder switch side and the output of the Guffa Anno. This will be explained in detail based on the drawings.

FIG. 2 shows a first embodiment of the present invention, in which 201 is P
CM signal, 202 is a reference power supply voltage switching switch, 20
3 is a code conversion circuit, 204, 205 is a ladder reset switch, 206, 207 is a guffaang, 208,
209 is an offset correction switch. Here, the first offset correction switch 20B is one contact point (hereinafter referred to as a "point") of the sub-C ladder switches SBI to SB4.

The other contact point is called a) and GND, and the second offset correction switch 209 is connected between point b and Guffa amplifier 20.
It is inserted between the output of 6. Other components that are the same as those in FIG. 1 are designated by the same reference numerals.

As explained in FIG. 1, the B1 bit of the 8-bit PCM signal 201 is set to the reference power supply voltage (+Vre
A switch 20 for changing the polarity of f or -”ref)
2 to switch the polarity of the output signal of the decoder. The remaining bits B2 to B8 are input to the code conversion circuit 203, and the bits B2 to B4 () are converted to the 8-bit codes SAI to SA8 as shown in Table 1 (,) above, and similarly B5 to B8 bits are 5BI-8 as shown in the same table (b).
It is converted to the code B4 and controls the switch indicated by the symbol - in FIG.

The operation of this circuit will be explained below.

First, reset switches 204 and 205 are connected to GND. When the DC offset of the sub C ladder buffer amplifier 206 and the main C ladder buffer amplifier 2θ7 is zero, each amplifier output voltage becomes zero. At this time, when the main C ladder switches SAI to SA8 are connected to GND, the sub C ladder switches SBI to SB4 are connected to point b, and the offset correction switch 208 is closed, the main C ladder IC
The electric charge of each capacitor of A to 128CA and 3CB to 16CB of the sub-C ladder is discharged to zero.

Next, when the offset correction switch 208 is opened and the offset correction switch 209 is closed, the electrodes to which the switches SBI to SB4 of each capacitor of the sub-C ladder are connected (hereinafter referred to as the lower electrode) are connected to the sub-C ladder buffer. The potential is the same as the output potential of the amplifier 206, and a charge corresponding to the output voltage and capacitance ratio of the sub-C ladder buffer amplifier 206 is stored in each capacitor. When the DC offset of the subladder buffer amplifier is zero, the charge on each capacitor is also zero. Next, when the sub-C ladder reset switch 205 is opened, the offset correction switch 209 is opened, and then the offset correction switch 20B is closed, the lower electrode of each capacitor is connected to GND. At this time, when the charge of each capacitor is zero, the buffer amplifier 20
The voltage appearing at the electrode of each capacitor (hereinafter referred to as the upper electrode) connected to the input of 6 is zero. From this state, as explained in FIG. 1, the switch 202. SA1~SA8. The output voltage is V by operating sB1 to SB4. Generate ut.

Here, a DC offset voltage voltage V is applied to the sub-C ladder buffer amplifier 206. ff, reset switches 204, 205 . When the offset correction switch 208 is closed and each C2 driver is reset, the output voltage of the sub-C ladder buffer is +Voff, and the lower electrode of each capacitor of the sub-C ladder is connected to the buffer amplifier 206, and each capacitor has a voltage of 3CB'. off + 2C
B ”off + 4 CB-VoH+8CB-vof
A charge of f, 160B-Voff is stored.

Next, when the reset switch 205 is opened, the offset correction switch 209 is opened, and then the offset correction switch 20B is closed, a voltage of -Voff is generated at the upper electrode of each capacitor. This voltage cancels the DC offset voltage of the buffer amplifier 206, so eventually,
The output voltage of bassoor amplifier 206 becomes zero. In this state, open the main C ladder reset switch 204 and reset the PC.
Each switch 202 . SAI～SA
8. If SB1 to SB4 are operated, the output voltage V is not affected by the DC offset of the sub-C ladder buffer amplifier 206. ut is obtained.

The voltage Vtop of the upper electrode of the sub-C ladder at this time is expressed by the following equation.

However, SBi takes the value of Pa1'' or 0# according to Table 1(b).

Also, the output voltage of the sub-ladder buffer amplifier 206 is: ■sB ” Vtop +Voff
---゛-direct 5), so in the end the sub-ladder output voltage v8
B becomes irrelevant to the DC offset voltage of the buffer amplifier 2θ6.

Although the decoder has been described above, similar results can be obtained with a local decoder used in a feedback encoder.

As explained above, in the first embodiment, by adding two switches to the conventional circuit, the DC offset voltage of the sub-ladder buffer amplifier used inside the decoder is stored in the sub-C ladder, and the offset voltage of the amplifier is The advantage of this method is that it is possible to create a highly accurate and stable encoder/decoder that is not affected by the DC offset voltage of the amplifier.

In the first embodiment, correction of the DC offset of the buffer amplifier of the sub-C ladder was explained, but if the DC offset of the buffer amplifier of the main C ladder becomes a problem in the decoder, the correction as shown in FIG. , offset correction switches 310 and 311 of the buffer amplifier 207
Offset correction switch 3 of buffer amplifier 306
It is sufficient to insert it corresponding to the connection relationship similar to 08°309. In this way, the DC offset of the buffer amplifier of the shift-in C ladder can be corrected by the same means as in the case of the sub-C ladder. 1st. In the second embodiment, a companding type decoder has been described, but as shown in FIG. Needless to say. As explained in detail above, this invention has a means for correcting the DC offset voltage of the buffer amplifier, so it has the advantage of not having to take the offset voltage of the amplifier into account, and requires less additional circuitry. Therefore, it can be used in high-precision encoders and decoders.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional C ladder decoder, Fig. 2 is a circuit diagram of a first embodiment of the present invention, Fig. 3 is a circuit diagram of a second embodiment of the present invention, and Fig. 4 is a circuit diagram of a conventional C ladder decoder. 3A and 3B respectively show circuit diagrams of a third embodiment of the present invention. 2o 1-PCM signal, 202. , '102--Switch for changing the polarity of the reference power supply, 206, 207゜3
06.307...Buffer amplifier, 208, 209
゜308, 309, 310, 311...Offset correction switch. Patent applicant Oki Electric Industry Co., Ltd. Nippon Telegraph and Telephone Public Corporation

Claims (1)

[Claims] The PCM signal is converted into an analog signal by switching the other ends of a plurality of capacitors, whose one ends are commonly connected and connected to a buffer amplifier, to the reference power supply and ground via a changeover switch in response to the PCM signal. encoder/
In the decoder, an offset correction switch is provided between the ground side contact of the changeover switch and the output end of the buffer amplifier, and between the ground side contact of the changeover switch and the ground. Encoder/decoder.