JP7183724B2 - D/A conversion circuit and A/D conversion circuit - Google Patents

Description

The present invention relates to a D/A conversion circuit and an A/D conversion circuit.

Among the D/A conversion circuits, there are those used in ΔΣ (delta-sigma) modulation type A/D conversion circuits in which the possible output levels are set in five stages. In this device, three analog level voltages (Vrefp, Vcm, and Vrefm) of high, medium, and low are generally set as reference potentials.

Usually, among the three reference potentials, Vcm is set to the same potential as the operational amplifier reference potential (analog ground: AGND), and Vrefp and Vrefn are set so as to satisfy Vrefp+Vrefm=Vcm/2. That is, if Vcm=0V, then Vrefm=-Vrefp.

Then, when outputting an analog signal corresponding to "0" among the five output levels that can be output corresponding to the input digital signal in five stages (-2, -1, 0, 1, 2) , sample period, and hold period, Vcm corresponding to the analog ground potential is selected and output to the DAC capacitor.

In this case, the operational amplifier connected to the D/A conversion circuit is connected to the inverting input terminal because the non-inverting input terminal is set to the ground potential and the non-inverting input terminal and the inverting input terminal are virtually grounded. One end of the DAC capacitance is at ground potential. As described above, since Vcm=AGND (analog ground), when Vcm is selected as the reference potential of the D/A conversion circuit, ideally no potential difference should occur across the DAC capacitance.

In general, a capacitive element has electrical characteristics such that the capacitance value changes according to the potential difference applied across both ends. Therefore, when the potential of the inverting input terminal is different from AGND due to the offset of the amplifier connected to the output part of the DAC capacity, the capacity value depends on the offset and the potential difference between both ends of the capacitive element in the DAC capacity. charge is accumulated. During the hold period, the potential difference across the DAC capacitance varies greatly depending on the reference voltage, so the value of the DAC capacitance also varies depending on the selected reference voltage.

As a result, the amount of electric charge subtracted by the D/A conversion circuit also fluctuates. Due to the voltage characteristics of the capacitance value of the DAC capacitor and the offset of the operational amplifier, there is a possibility that the linearity of the A/D conversion characteristics may be degraded.

U.S. Pat. No. 7,388,533

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and its object is to reduce the adverse effects of the electrical characteristics of the capacitors provided therein, and to provide a high-speed and high-precision D/A conversion circuit and this D/A conversion circuit. An object of the present invention is to provide an A /D conversion circuit corresponding to an A conversion circuit.

The D/A conversion circuit according to claim 1 is a D/A conversion circuit having an output terminal connected to an input terminal of an operational amplifier connected to a quantization circuit (4), comprising a DAC capacitance (Cd), A reference potential (Vcm), a first voltage (Vrefp) higher than the reference potential, and a second voltage (Vrefm) lower than the reference potential are selectively applied to the input side of the DAC capacitor as analog potentials. selection switches (Sdt, Sdm, Sdb) for supplying a voltage, a ground switch (Sd2) for connecting the output side of the DAC capacitor to the analog ground potential, and an output switch (Sd3) for connecting the output side of the DAC capacitor to the output terminal and selectively connecting the selection switch to one of the potentials and turning on the ground switch in a first period corresponding to the value of the 4-level quantization result output from the quantization circuit to turn on the DAC in a second period following the first period, the select switch is selectively connected to either the first voltage or the second voltage, and the output switch is turned on to transfer the voltage from the DAC capacitor to the output terminal; , one of four levels of analog potential is output.

In the above configuration, the D/A conversion circuit selectively connects the selection switch to any potential in the first period for an input four-level input digital signal, charges the DAC capacity, and continues. In the second period, either Vrefp or Vrefm is selectively connected to output the potential of the DAC capacitor to the output terminal. As a result, even if Vcm is selected in the first period, the condition for selecting Vcm is not used in the second period. The influence can be reduced, and an analog potential can be output with high accuracy as an output.

The inventor considers the following points in order to obtain the above configuration and action.
That is, since a high-precision A/D conversion circuit generally uses a differential circuit configuration, even if the DAC capacitance has a voltage characteristic, if Vrefp (Vrefm) is selected for one side of the differential, Since the opposite side of the differential is Vrefm (Vrefp), the sum of the DAC capacitances on both sides of the differential is equal.

However, when Vcm is selected, the potentials at both ends of the DAC capacitance are affected by the offset, but the potentials are substantially the same. are different values due to the voltage characteristics. As a result, especially in the differential configuration, the amount of charge subtracted by the DAC capacitance varies due to the amplifier offset when Vrefp, Vrefm or Vcm is selected as the reference voltage in the second period. That is, the linearity of A/D conversion is degraded.

In this case, Vrefp and Vrefm are supplied from an external power supply, or the IC often has a dedicated external terminal, and the impedance between the input side of the DAC capacitance and the impedance between Vrefp and Vrefm is are often of low impedance, respectively. On the other hand, since Vcm is often generated by an amplifier inside the IC, the impedance between the input side of the DAC capacitance and Vcm tends to be higher than the impedance between Vrefp and Vrefm.

When Vcm is selected as the reference voltage, the switch for selecting Vcm is connected to the power supply for driving the switch and the ground (potential different from the analog ground, which is a negative potential if the analog ground is 0 V). ), in which case the on-resistance of the switch tends to increase. As a result, when Vcm is selected in the second period, the performance of the amplifier that generates Vcm and the on-resistance of the switch that selects Vcm are all affected, so there is a problem that the operating speed decreases. It came.

Therefore, in the present invention, the above problem can be avoided, so that high-speed and high-precision D/A conversion can be performed while avoiding technical problems dependent on the voltage characteristics of the output capacitance.

Electrical configuration diagram showing the first embodiment FIG. 4 is a diagram showing the relationship between phases and thresholds in A/D conversion; Diagram showing the operational relationship between sample and hold switches in the input circuit FIG. 4 is a diagram showing the operational relationship between the sample period and the hold period corresponding to the Qout value of the switch of the D/A conversion circuit; FIG. 4 is a diagram showing the relationship between the amplifier output voltage V1 and the amplifier output Vamp after first quantization; Operation explanatory diagram of the D/A conversion circuit corresponding to the first quantization Qout1 and the second quantization Qout2 FIG. 4 is a diagram showing the relationship between the amplifier output voltage V2 and the amplifier output Vamp after second quantization; A diagram showing the conditions for the first quantization in terms of threshold voltages A diagram showing the second quantization condition in terms of threshold voltage FIG. 11 is a diagram showing threshold voltages obtained by synthesizing the first and second quantization conditions. A diagram showing the synthesized first and second quantization conditions with reference voltages. FIG. 11 is a diagram showing the relationship between the amplifier output voltage V1 and the amplifier output Vamp after the first quantization, showing the second embodiment; FIG. 4 is a diagram showing the relationship between the amplifier output voltage V2 and the amplifier output Vamp after second quantization; FIG. 11 is a diagram showing threshold voltages obtained by synthesizing the first and second quantization conditions. A diagram showing the synthesized first and second quantization conditions with reference voltages. FIG. 11 is a diagram showing the relationship between the amplifier output voltage V1 and the amplifier output Vamp after the first quantization, showing the third embodiment; FIG. 4 is a diagram showing the relationship between the amplifier output voltage V2 and the amplifier output Vamp after second quantization; FIG. 11 is a diagram showing threshold voltages obtained by synthesizing the first and second quantization conditions. A diagram showing the synthesized first and second quantization conditions with reference voltages.

(First embodiment)
A first embodiment in which the D/A conversion circuit of the present invention is used in a ΔΣ modulation type A/D conversion circuit will be described below with reference to FIGS. 1 to 11. FIG.
In FIG. 1, a ΔΣ modulation type A/D conversion circuit (hereinafter simply referred to as an A/D conversion circuit) 1 has an input terminal 1a for an analog input Vin and an output terminal 1b for a digital output Dout. The A/D conversion circuit 1 includes an input circuit 2, an integration circuit 3, a quantization circuit 4, a control circuit 5 and a D/A conversion circuit 6.

The input circuit 2 has a sampling capacitor Cs and four switches Ss1 to Ss4. Input terminal 1a is connected to integration circuit 3 via switch Ss1, capacitor Cs and switch Ss3 in series. Input and output sides of the capacitor Cs are connected to an analog ground AGND (hereinafter simply referred to as AGND) via switches Ss4 and Ss2, respectively. The four switches Ss1 to Ss4 are controlled to turn on and off by the control circuit 5 . Here, AGND can be arbitrarily set, and is not limited to 0V as described in this embodiment.

By turning on the switches Ss1 and Ss2 and turning off the switches Ss3 and Ss4, one end of the sampling capacitor Cs on the integrating circuit 3 side is electrically disconnected from the integrating circuit 3 and connected to AGND. As a result, charges corresponding to the analog input Vin are accumulated in the sampling capacitor Cs. Also, the switches Ss1 and Ss2 are turned off and the switches Ss3 and Ss4 are turned on, whereby the charge accumulated in the sampling capacitor Cs is transferred to the feedback capacitor Cf of the integration circuit 3.

The integration circuit 3 includes an amplifier 31 and a feedback capacitor Cf. The inverting input terminal of the amplifier 31 is connected to the switch Ss3 of the input circuit 2 and to the output terminal via the capacitor Cf. A non-inverting input terminal of the amplifier 31 is connected to the analog ground. AGND is the reference potential of the amplifier 31 and thus the reference potential of the entire A/D conversion circuit 1 .

The quantization circuit 4 comprises five comparators 41-45. Threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- are applied to the inverting input terminals of the five comparators 41 to 45, respectively. The non-inverting input terminals of the five comparators 41 to 45 are commonly connected to the output terminal of the amplifier 31 .

The comparators 41 to 45 compare the output voltage Vamp of the amplifier with the respective threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- and output the result as a quantization result Qout to the control circuit 5, which will be described later. In this embodiment, quantization results Qout of four levels "2", "1", "-1" and "-2" are output.

The control circuit 5 outputs a control signal corresponding to the quantization result Qout to the D/A conversion circuit 6, which will be described later, and outputs the result of performing signal processing such as integration or filtering on the quantization result Qout to A/D. Output to the output terminal 1b as the conversion result Dout.

The five threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- are generated by a threshold generation circuit (not shown). In this case, Vth0 is a reference threshold and is set to the AGND level, and Vth1+ is a positive first threshold and is set to a potential higher than Vth0 by a first voltage. Vth2+ is a positive second threshold and is set to a potential higher than Vth1+ and higher than Vth0 by a second voltage. Vth1- is a negative first threshold, and is set to a potential lower than Vth0 by a first voltage. Vth2- is a second negative threshold and is set to a potential lower than Vth1- and lower than Vth0 by a second voltage.

When the AGND level is 0V, Vth1+ and Vth1- have the same absolute value Vth1, which is the first voltage, and have the same positive and negative levels. Set to large positive and negative levels. Also, as will be described later, Vth1 and Vth2 are set at levels related to the reference voltage Vref.

The D/A conversion circuit 6 has a DAC capacitor Cd and five switches Sdt, Sdm, Sdb, Sd2 and Sd3. In the D/A conversion circuit 6, three analog potentials Vrefp, Vrefm, and Vcm are set as reference potentials. For example, the reference potential Vcm is set to AGND, Vrefp is set to a potential higher than AGND, and Vrefm is set to a potential lower than AGND.

When AGND is 0V, Vrefp and Vrefm have the same absolute value and opposite polarities, and are set so as to satisfy Vrefp=-Vrefm. The switches Sdt, Sdm, and Sdb function as selection switches and connect Vrefp, Vcm, and Vrefm to the input side of the DAC capacitor Cd, respectively. That is, the potential on the input side of the DAC capacitor Cd is equal to one of Vrefp, Vrefm or Vcm exclusively selected by the switches Sdt, Sdm and Sdb.

The output side of the DAC capacitor Cd is connected to AGND via a switch Sd2 and to the intermediate point between the inverting input terminal of the amplifier 31 and the feedback capacitor Cf via a switch Sd3. The five switches Sdt, Sdm, Sdb, Sd2, and Sd3 are on/off controlled by the control circuit 5 .

In this case, control circuit 5 performs a sample operation and a hold operation based on the signal applied from quantization circuit 4. FIG. In the sample operation, the control circuit 5 turns on the switch Sd2 while turning off the switch Sd3, and turns on any one of the selection switches Sdt, Sdm, and Sdb to accumulate a predetermined charge. In the hold operation, the control circuit 5 turns on the switch Sd3 while turning off the switch Sd2, and turns on either the selection switch Sdt or Sdb.

As a result, the charge accumulated in the DAC capacitor Cd during the sampling operation period and the charge corresponding to the potential on the input side of the DAC capacitor Cd determined by turning on either the switch Sdt or Sdb are transferred to the feedback capacitor Cf. transferred. That is, the D/A conversion circuit 6 performs subtraction according to the quantization result Qout.

FIG. 2 shows the relationship between the phase and the threshold voltage in the A/D conversion processing of the analog potential Vin by the A/D conversion circuit 1. In FIG. Phases indicate first quantization and second quantization, respectively, and indicate threshold voltages used in the sample operation and hold operation in each phase. Here, in the first quantization, the quantization circuit 4 uses all five threshold voltages Vth2+, Vth1+, Vth0, Vth1-, Vth2-. In the second quantization, the quantization circuit 4 uses three threshold voltages Vth1+, Vth0, and Vth1-.

In the above configuration, in this embodiment, for example, the sampling capacitor Cs and the feedback capacitor Cf are set to the same capacitance value, and the DAC capacitor Cd is set to 1/8 the capacitance value of the feedback capacitance Cf.
Cs=Cf
Cd=Cf/8

Furthermore, the five threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- described above as threshold voltages are voltages generated by dividing the reference voltage Vref and set as follows.

Vth2+=7/16×Vref(V)
Vth1+=3/16×Vref(V)
Vth0=0 (V)
Vth1-=-3/16×Vref(V)
Vth2-=-7/16×Vref(V)

Next, the operation of the above configuration will be described with reference to FIGS. 3 to 10 as well. First, the basic operation of each switch in the input circuit 2 and the D/A conversion circuit 5 will be described.

In the control circuit 5, the combination of the switch control and the selected reference voltage in the sample period, which is the first period, and the hold period, which is the second period, according to the quantization circuit output Qout given from the quantization circuit 4 is shown in FIG. Execute as shown.

First, when the value of Qout is "2", the control circuit 5 turns on the switches Sdb and Sd2 and turns off the switches Sdm, Sdt, and Sd3 during the sample period. As a result, the input side of the DAC capacitance Cd is connected to Vrefm of "L" and the output side is connected to AGND, so that the DAC capacitance Cd is charged with Vrefm-AGND.

Next, during the hold period, switches Sdt and Sd3 are turned on, and switches Sdb, Sdm and Sd2 are turned off. As a result, the input side of the DAC capacitor Cd is connected to Vrefp of “H”, and the output side is connected to the inverting input terminal of the amplifier 31 . As a result, the charge corresponding to the potential difference Vrefm−Vrefp of the reference voltages selected in each period is transferred from the DAC capacitor Cd to the feedback capacitor Cf.

Also, when the value of Qout is "1", the control circuit 5 turns on the switches Sdm and Sd2 and turns off the switches Sdt, Sdb, and Sd3 during the sample period. As a result, the input side of the DAC capacitance Cd is connected to Vcm of "0", and the output side is connected to AGND, so if Vcm=AGND, the DAC capacitance Cd maintains a state of 0 V across the terminals.

Next, during the hold period, switches Sdt and Sd3 are turned on, and switches Sdb, Sdm and Sd2 are turned off. As a result, the input side of the DAC capacitor Cd is connected to Vrefp of “H”, and the output side is connected to the inverting input terminal of the amplifier 31 . By this. A charge corresponding to the potential difference Vcm−Vrefp of the reference voltage selected in each period is transferred from the DAC capacitor Cd to the feedback capacitor Cf.

Also, when the value of Qout is "-1", the control circuit 5 turns on the switches Sdm and Sd2 and turns off the switches Sdt, Sdb, and Sd3 during the sample period. As a result, the input side of the DAC capacitance Cd is connected to Vcm of "0", and the output side is connected to AGND, so if Vcm=AGND, the DAC capacitance Cd maintains a state of 0 V across the terminals.

Next, during the hold period, switches Sdb and Sd3 are turned on, and switches Sdt, Sdm and Sd2 are turned off. As a result, the input side of the DAC capacitor Cd is connected to Vrefm of “L”, and the output side is connected to the non-inverting input terminal of the amplifier 31 . By this. A charge corresponding to the potential difference Vcm−Vrefm of the reference voltage selected in each period is transferred from the DAC capacitor Cd to the feedback capacitor Cf.

When the value of Qout is "-2", the control circuit 5 turns on the switches Sdt and Sd2 and turns off the switches Sdb, Sdm, and Sd3 during the sample period. As a result, the input side of the DAC capacitance Cd is connected to Vrefp of "H" and the output side is connected to AGND, so that the DAC capacitance Cd is charged with Vrefp-AGND.

Next, during the hold period, switches Sdb and Sd3 are turned on, and switches Sdt, Sdm and Sd2 are turned off. As a result, the input side of the DAC capacitor Cd is connected to Vrefm of “L”, and the output side is connected to the non-inverting input terminal of the amplifier 31 . By this. A charge corresponding to the potential difference Vrefp-Vrefm of the reference voltage selected in each period is transferred from the DAC capacitor Cd to the feedback capacitor Cf.

In the above case, the voltage fed back from the D/A conversion circuit 6 to the output voltage of the amplifier is selected in each of the sample period and the hold period from the ratio of the DAC capacitance Cd and the feedback capacitance Cf, as described above. A voltage corresponding to 1/8 of the potential difference of the reference voltage is obtained. In addition, since a differential circuit configuration is generally employed, the potential difference of the selected reference voltage is doubled.

That is, when Vref=(Vrefp−Vcm)×2=(Vcm−Vrefm)×2, when the potential difference of the selected reference voltage is Vcm−Vrefm or Vrefp−Vrefm, Vref/8 or Vref/4 is It is added to the output voltage of the amplifier, and in the case of Vcm-Vrefp or Vrefm-Vrefp, Vref/8 or Vref/4 is subtracted from the output voltage of the amplifier.

Next, the contents of the first D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 5, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V1 before D/A conversion and V2 after D/A conversion.

Here, if the amplifier output voltage V1 before D/A conversion is first quantized with five threshold voltages as described above in the quantization circuit 4, the magnitude of the amplifier output voltage V1 is As shown in FIG. 8, a quantized output Qout1 of four levels of "2", "1", "-1" and "-2" is obtained according to . Based on this result, adding the amplifier output voltage V1 to the output from the D/A conversion circuit 6 yields the following result.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the first quantized value Qout1. That is, when Qout1 is "2", it is "L" during the sample period and "H" during the hold period. When Qout1 is "1", it is "0" during the sample period and "H" during the hold period. When Qout1 is "-1", it is "0" during the sample period and "L" during the hold period. When Qout1 is "-2", it is "H" during the sample period and "L" during the hold period.

Therefore, by adding the output of the D/A conversion circuit 6 resulting from the first quantization to the amplifier output voltage V1, the amplifier output voltage V2 can be obtained as indicated by the thick solid line in FIG. In this case, the output Qout1 of the first quantization is "-1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth0 and less than the threshold Vth1+, and is "1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth1- and less than the threshold Vth0. .

In the above case, regardless of the value of the quantization result Qout, the potential of the DAC capacitor Cd is output to the input terminal of the amplifier 31 so that Vcm is not selected as the reference voltage during the hold period. Even if the capacitance Cd has voltage characteristics, it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 .

Next, the contents of the second D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 7, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V2 after the first D/A conversion and V3 after the second A/D conversion.

Here, when the amplifier output voltage V2 before D/A conversion is subjected to the second quantization with three threshold voltages as described above in the quantization circuit 4, the magnitude of the amplifier output voltage V2 becomes Accordingly, as shown in FIG. 9, four levels of quantized output Qout2 of "2", "1", "-1" and "-2" are obtained. Based on this result, adding the amplifier output voltage V2 to the output from the D/A conversion circuit 6 yields the following result. In this case, in the second quantization, as shown in FIG. 9, the amplifier output voltage V2 is divided into four levels and the quantized output Qout2 is output without using the thresholds Vth2+ and Vth2-.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the second quantization value Qout2, as in the case of the first quantization. That is, when Qout2 is "2", it is "L" during the sample period and "H" during the hold period. When Qout2 is "1", it is "0" during the sample period and "H" during the hold period. When Qout2 is "-1", it is "0" during the sample period and "L" during the hold period. When Qout2 is "-2", it is "H" during the sample period and "L" during the hold period. Therefore, by adding the output of the D/A conversion circuit 6 resulting from the second quantization to the amplifier output voltage V2, the amplifier output voltage V3 can be obtained as indicated by the thick solid line in FIG.

In the above case, similarly to the first D/A conversion, regardless of the value of the quantization result Qout, Vcm is not selected as the reference voltage during the hold period, and the potential of the DAC capacitor Cd is increased by the amplifier 31. Therefore, even if the DAC capacitance Cd has voltage characteristics, it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 .

By executing quantization and D/A conversion processing twice as described above, it is possible to output 9-level quantization results. Also, in this case, the D/A conversion circuit 5 does not perform the operation of selecting Vcm during the hold period, so it is possible to avoid the occurrence of an error in the electrical characteristics of the DAC capacitance Cd due to the offset of the amplifier 31. Therefore, accurate A/D conversion can be performed.

Next, with reference to FIG. 8 to FIG. 11, a summary of the operations in the two quantization and D/A conversion processes described above will be described. As described above, in the first quantization, a four-level quantization result Qout1 is output with five threshold voltages for the amplifier output voltage V1 as shown in FIG. In the second quantization, as shown in FIG. 9, a four-level quantization result Qout2 is output with three threshold voltages for the amplifier output voltage V2.

Here, the amplifier output voltage V2 before the second D/A conversion is the result of calculating the difference between the output of the D/A conversion circuit 6 and the amplifier output voltage V1 before the first D/A conversion. Therefore, the output reference voltage Vref of the D/A conversion circuit 6 can be used to express the following equation (1).
Also, since Vref×Cd/Cf is a constant value, if it is set to VR, the equation (1) can be expressed in a simplified expression as the following equation (2).
V2=V1-Qout1*Vref*Cd/Cf (1)
V2=V1-Qout1×VR (2)

Here, in the first quantization, as shown in FIG. 8, 6 determination conditions are set by 5 threshold voltages. At this time, for example, if the condition indicated by symbol 1b is met, there is a possibility that two conditions indicated by symbols 2a and 2b in FIG. 9 may be met in the second quantization.

That is, although the second quantization corresponds to the amplifier output voltage V2, the conditions 2a and 2b are rewritten using V1 shown in Equation (2). First, since the condition of the symbol 2a is the following formula (3), substituting the formula (2) into this results in the following formula (4).
Condition of symbol 2a: V2≧Vth1+ (3)
→V1−Qout1×VR≧Vth1+ (4)
Condition of symbol 2b: Vth1+>V2≧Vth0 (5)
→Vth1+>V1−Qout1×VR≧Vth0 (6)

Therefore, when the first quantized amplifier output voltage V1 satisfies the condition of the symbol 1b, that is, the following equation (7), Qout1 is "1", so the conditions of the symbols 2a and 2b are changed to the amplifier output voltage V1 When rewritten as the condition of , the equations (8) and (9) are obtained.
Vth2+>V1≥Vth1+ (7)
Condition of symbol 2a: V1-VR≧Vth1+
→V1≧Vth1++VR (8)
Condition of symbol 2b: Vth1+>V1-VR≧Vth0
→Vth1++VR>V1≧Vth0+VR (9)

As a result, when the condition of symbol 1b of the first quantization is satisfied, the conditions of symbols 2a and 2b of the second quantization are represented by the amplifier output voltage V1, and the following equations (10) and (11) are obtained.
Condition of symbol 2a: Vth2+>V1≧Vth1++VR (10)
Condition 2b: Vth1++VR>V1≧Vth1+ (11)

If other symbols are rewritten in the same way, by outputting quantization values Qout2 that differ from each other in the parts divided into two levels, finally, as shown in FIG. It becomes possible to obtain the output of the quantization level.

Further, if the five threshold voltages described above are rewritten in relation to the reference voltage Vref described above, all conditions can be set as divided voltages of the reference voltage Vref as shown in FIG.

According to the first embodiment as described above, the D/A conversion circuit 6 performs four-level analog conversion based on the four-level quantization result Qout values "2", "1", "-1", and "-2". It is configured to output a potential. At this time, even if the D/A conversion circuit 6 selects Vcm corresponding to AGND during the sample period, it does not select Vcm during the hold period. It is possible to suppress the occurrence of errors due to the electrical characteristics of As a result, a highly accurate analog potential can be output.

Further, by using the 4-level D/A conversion circuit 6 twice, the A/D conversion circuit 1 can finally obtain a 9-level output.
According to this embodiment, as described above, the D/A conversion circuit 6 does not use Vcm of the AGND potential, which becomes a high impedance, during the hold period, so it is possible to suppress a decrease in operating speed.

Furthermore, in the operation of the D/A conversion circuit 6, since Vcm which is the AGND potential is not continuously used during the sample period and the hold period, the output of the amplifier 31 is not fixed at the same level, and the dithering function is achieved. be able to fulfill

(Second embodiment)
12 to 15 show the second embodiment, and the differences from the first embodiment will be explained below. In this embodiment, the conditions for setting five threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- are changed.

More specifically, two threshold voltages Vth2+ and Vth2- of the threshold voltages are set as follows as values different from those in the first embodiment.
Vth2+=5/16×Vref(V)
Vth2-=-5/16×Vref(V)

Next, the contents of the first D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 12, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V1 before D/A conversion and V2 after D/A conversion.

When the amplifier output voltage V1 before D/A conversion is subjected to the first quantization (hereinafter referred to as first quantization) with five threshold voltages in the quantization circuit 4, the amplifier output voltage V1 As shown in FIG. 8, four levels of quantization output Qout1 of "2", "1", "-1", and "-2" are obtained according to the magnitude of . Based on this result, adding the amplifier output voltage V1 to the output from the D/A conversion circuit 6 yields the following result.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the first quantized output Qout1. Therefore, by adding the output of the D/A conversion circuit 6 resulting from the first quantization to the amplifier output voltage V1, the amplifier output voltage V2 can be obtained as indicated by the thick solid line in FIG. In this case, the first quantized output Qout1 is "-1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth0 and less than the threshold Vth1+, and is "1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth1- and less than the threshold Vth0.

In the above case, regardless of the value of the quantization result Qout, the potential of the DAC capacitor Cd is output to the input terminal of the amplifier 31 so that Vcm is not selected as the reference voltage during the hold period. Even if the capacitance Cd has voltage characteristics, it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 .

Next, the contents of the second D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 13, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V2 after the first D/A conversion and V3 after the second A/D conversion.

Here, when the amplifier output voltage V2 before D/A conversion is subjected to the second quantization with three threshold voltages as described above in the quantization circuit 4, the magnitude of the amplifier output voltage V2 becomes Accordingly, four levels of quantized output Qout2 of "2", "1", "-1" and "-2" are obtained. Based on this result, adding the amplifier output voltage V1 to the output from the D/A conversion circuit 6 yields the following result. In this case, in the second quantization, as shown in FIG. 9, the amplifier output voltage V2 is divided into four levels and the quantized output Qout2 is output without using the thresholds Vth2+ and Vth2-.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the second quantization value Qout2, as in the case of the first quantization. Therefore, by adding the output of the D/A conversion circuit 6 resulting from the second quantization to the amplifier output voltage V2, the amplifier output voltage V3 can be obtained as indicated by the thick solid line in FIG. In this case, as in the first D/A conversion, regardless of the value of the quantization result Qout, Vcm is not selected as the reference voltage during the hold period, and the potential of the DAC capacitor Cd is applied to the input terminal of the amplifier 31. , it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 even when the DAC capacitance Cd has voltage characteristics.

By executing quantization and D/A conversion processing twice as described above, it is possible to output 9-level quantization results. Further, in this case, the D/A conversion circuit 6 does not perform the operation of selecting Vcm during the hold period, so it is possible to avoid the occurrence of an error in the electrical characteristics of the DAC capacitance Cd due to the offset of the amplifier 31. Therefore, accurate A/D conversion can be performed.

Next, with reference to FIG. 14 and FIG. 15, a summary of the operations in the two quantization and D/A conversion processes described above will be described. As described above, in the first quantization, a four-level quantization result Qout1 is output with five threshold voltages for the amplifier output voltage V1 as shown in FIG. In the second quantization, as shown in FIG. 9, a four-level quantization result Qout2 is output with three threshold voltages for the amplifier output voltage V2.

Here, the amplifier output voltage V2 before the second D/A conversion is the result of calculating the difference between the output of the D/A conversion circuit 6 and the amplifier output voltage V1 before the first D/A conversion. Therefore, by using the output reference voltage Vref of the D/A conversion circuit 6, it can be expressed as the above-mentioned equation (1), and if Vref×Cd/Cf=VR, it can be expressed as the above-mentioned equation (2). can be done.

Here, in the first quantization, as shown in FIG. 8, 6 determination conditions are set by 5 threshold voltages. At this time, for example, if the condition indicated by symbol 1a is satisfied, there is a possibility that two conditions indicated by symbols 2a and 2b in FIG. 9 may be satisfied in the second quantization.

That is, although the second quantization corresponds to the amplifier output voltage V2, the conditions 2a and 2b are rewritten using V1 shown in Equation (2). First, since the condition of the symbol 2a is the following formula (12), substituting the formula (2) into this results in the following formula (13). Similarly, the condition of symbol 2b is given by the following formula (14), so substituting the formula (2) into this results in the following formula (15).
Condition of symbol 2a: V2≧Vth1+ (12)
→V1−Qout1×VR≧Vth1+ (13)
Condition of symbol 2b: Vth1+>V2≧Vth0 (14)
→Vth1+>V1−Qout1×VR≧Vth0 (15)

Therefore, when the first quantized amplifier output voltage V1 satisfies the condition of symbol 1a, that is, the following equation (16), Qout1 is "2", so the conditions of symbols 2a and 2b are changed to the amplifier output voltage V1 is rewritten as the condition, the equations (16) and (17) are obtained.
V1≧Vth2+ (16)
Condition of symbol 2a: V1-2VR≧Vth1+
→V1≧Vth1++2VR (17)
Condition 2b: Vth1+>V1-2VR≧Vth0
→Vth1++2VR>V1≧Vth0+2VR (18)

As a result, when the condition of symbol 1a of the first quantization is satisfied, the conditions of symbols 2a and 2b of the second quantization are represented by the amplifier output voltage V1, and the following equations (19) and (20) are obtained.
Condition of symbol 2a: V1≧Vth1++2VR (19)
Condition of symbol 2b: Vth1++2VR>V1≧Vth2+ (20)

If other symbols are rewritten in the same way, by outputting quantization values Qout2 that are different from each other for the parts divided into two levels, finally, as shown in FIG. It becomes possible to obtain the output of the quantization level.

Further, if the five threshold voltages described above are rewritten in relation to the reference voltage Vref described above, all conditions can be set as divided voltages of the reference voltage Vref as shown in FIG.
Also by such a second embodiment, it is possible to obtain the same effects as those of the first embodiment.

(Third Embodiment)
16 to 19 show the third embodiment, and the differences from the second embodiment will be explained below. In this embodiment, the conditions for setting five threshold voltages Vth2+, Vth1+, Vth0, Vth1-, and Vth2- are changed.

More specifically, two threshold values Vth2+ and Vth2- of the threshold voltages are set as follows as values different from those in the first embodiment.
Vth2+ = 6/16 x Vref (V)
Vth2-=-6/16×Vref(V)

Next, the contents of the first D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 16, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V1 before D/A conversion and V2 after D/A conversion.

When the amplifier output voltage V1 before D/A conversion is subjected to the first quantization with five threshold voltages in the quantization circuit 4, the following values are obtained according to the magnitude of the amplifier output voltage V1 as shown in FIG. A quantized output Qout1 of four levels of "2", "1", "-1" and "-2" is obtained. Based on this result, adding the amplifier output voltage V1 to the output from the D/A conversion circuit 6 yields the following result.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the first quantized value Qout1. Therefore, by adding the output of the D/A conversion circuit 6 resulting from the first quantization to the amplifier output voltage V1, the amplifier output voltage V2 can be obtained as indicated by the thick solid line in FIG. In this case, the output Qout1 of the first quantization is "-1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth0 and less than the threshold Vth1+, and is "1" when the amplifier output voltage V1 is greater than or equal to the threshold Vth1- and less than the threshold Vth0. .

In the above case, regardless of the value of the quantization result Qout, the potential of the DAC capacitor Cd is output to the input terminal of the amplifier 31 so that Vcm is not selected as the reference voltage during the hold period. Even if the capacitance Cd has voltage characteristics, it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 .

Next, the contents of the second D/A conversion process by the D/A conversion circuit 6 will be described. As shown in FIG. 17, the relationship between the input potential Vin and the output voltage Vamp of the amplifier 31 is V2 after the first D/A conversion and V3 after the second A/D conversion.

Here, when the amplifier output voltage V2 before D/A conversion is subjected to the second quantization with three threshold voltages as described above in the quantization circuit 4, the magnitude of the amplifier output voltage V2 becomes Accordingly, four levels of quantized output Qout2 of "2", "1", "-1" and "-2" are obtained. Based on this result, adding the amplifier output voltage V1 to the output from the D/A conversion circuit 6 yields the following result. In this case, in the second quantization, as shown in FIG. 9, the amplifier output voltage V2 is divided into four levels and the quantized output Qout2 is output without using the thresholds Vth2+ and Vth2-.

The D/A conversion circuit 6 performs the operation shown in FIG. 6 for the second quantization value Qout2, as in the case of the first quantization. Therefore, by adding the output of the D/A conversion circuit 6 resulting from the second quantization to the amplifier output voltage V2, the amplifier output voltage V3 can be obtained as indicated by the thick solid line in FIG. In this case, as in the first D/A conversion, regardless of the value of the quantization result Qout, Vcm is not selected as the reference voltage during the hold period, and the potential of the DAC capacitor Cd is applied to the input terminal of the amplifier 31. , it is possible to suppress the occurrence of an output error due to the offset of the amplifier 31 even when the DAC capacitance Cd has voltage characteristics.

By executing quantization and D/A conversion processing twice as described above, it is possible to output 9-level quantization results. Further, in this case, the D/A conversion circuit 6 does not perform the operation of selecting Vcm during the hold period, so it is possible to avoid the occurrence of an error in the electrical characteristics of the DAC capacitance Cd due to the offset of the amplifier 31. Therefore, accurate A/D conversion can be performed.

Next, with reference to FIG. 18 and FIG. 19, a summary of the operations in the two quantization and D/A conversion processes described above will be described. As described above, in the first quantization, a four-level quantization result Qout1 is output with five threshold voltages for the amplifier output voltage V1 as shown in FIG. In the second quantization, as shown in FIG. 9, a four-level quantization result Qout2 is output with three threshold voltages for the amplifier output voltage V2.

Here, the amplifier output voltage V2 before the second D/A conversion is the result of calculating the difference between the output of the D/A conversion circuit 5 and the amplifier output voltage V1 before the first D/A conversion. Therefore, using the output reference voltage Vref of the D/A conversion circuit 6, the above equation (1) can be expressed. can be done.

Here, in the first quantization, as shown in FIG. 8, 6 determination conditions are set by 5 threshold voltages. At this time, for example, if the condition indicated by symbol 1a is satisfied, the conditions indicated by symbols 2a and 2b of the second quantization are represented by the amplifier output voltage V1 in the same manner as in the second embodiment. , (20).

For example, when the condition indicated by symbol 1b is met, there is a possibility that the second quantization may meet two conditions indicated by symbols 2a and 2b shown in FIG. That is, although the second quantization corresponds to the amplifier output voltage V2, the conditions 2a and 2b are rewritten using the amplifier output voltage V1 shown in Equation (2). First, since the condition of the symbol 2a is the following formula (21), substituting the formula (2) into this results in the following formula (22). Similarly, the condition of symbol 2b is given by the following formula (23), so substituting the formula (2) into this results in the following formula (24).

Condition of symbol 2a: V2≧Vth1+ (21)
→V1−Qout1×VR≧Vth1+ (22)
Condition of symbol 2b: Vth1+>V2≧Vth0 (23)
→Vth1+>V1−Qout1×VR≧Vth0 (24)

Therefore, when the first quantized amplifier output voltage V1 satisfies the condition of the symbol 1b, that is, the following equation (7), Qout1 is "1", so the conditions of the symbols 2a and 2b are changed to the amplifier output voltage V1 is rewritten as the condition, the equations (25) and (26) are obtained.

Vth2+>V1≥Vth1+ (7)
Condition of symbol 2a: V1-VR≧Vth1+
→V1≧Vth1++VR (25)
Condition of symbol 2b: Vth1+>V1-VR≧Vth0
→Vth1++VR>V1≧Vth0+VR (26)

Thus, when the condition of symbol 1b of the first quantization is satisfied, the conditions of symbols 2a and 2b of the second quantization are represented by the input V1, and the following equations (27) and (28) are obtained.
Condition of symbol 2a: Vth2+>V1≧Vth1++VR (27)
Condition 2b: Vth1++VR>V1≧Vth1+ (28)

If other symbols are rewritten in the same way, by outputting quantization values Qout2 that differ from each other in the parts divided into two levels, finally, as shown in FIG. It becomes possible to obtain the output of the quantization level.
Further, if the five threshold voltages described above are rewritten in relation to the reference voltage Vref described above, all conditions can be set as divided voltages of the reference voltage Vref as shown in FIG.

Also by such a third embodiment, it is possible to obtain the same effects as those of the first embodiment. Further, in the third embodiment, the threshold voltages Vth2+ and Vth2- are set to be integral multiples of the threshold voltages Vth1+ and Vth1-, respectively, so that the threshold voltage generation circuit can be simplified. .

(Other embodiments)
Although the present disclosure has been described with reference to examples, it is understood that the present disclosure is not limited to such examples or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

In the drawings, 1 is an A/D conversion circuit, 2 is an input circuit, 3 is an integration circuit, 4 is a quantization circuit, 5 is a control circuit, 6 is a D/A conversion circuit, 31 is an amplifier, 41 to 45 are comparators, Cs is a sampling capacitor, Cf is a feedback capacitor, Cd is a DAC capacitor, Ss1 to Ss4 are switches, Sdt, Sdm and Sdb are selection switches, Sd2 is a ground switch, and Sd3 is an output switch.

Claims (8)

A D/A conversion circuit whose output terminal is connected to the input terminal of an operational amplifier connected to a quantization circuit (4),
DAC capacity (Cd);
A reference potential (Vcm), a first voltage (Vrefp) higher than the reference potential, and a second voltage (Vrefm) lower than the reference potential are selectively applied to the input side of the DAC capacitor as analog potentials. selection switches (Sdt, Sdm, Sdb) that provide
a ground switch (Sd2) that connects the output side of the DAC capacitor to an analog ground potential;
An output switch (Sd3) that connects the output side of the DAC capacity to an output terminal,
According to the value of the four-level quantization result output from the quantization circuit, the selection switch is selectively connected to any potential and the ground switch is turned on in the first period to charge the DAC capacitance. In a second period following the first period, the selection switch is selectively connected to either the first voltage or the second voltage, the output switch is turned on, and four levels are supplied from the DAC capacitor to the output terminal. A D/A conversion circuit (6) for outputting any analog potential. The value of the 4-level quantization result is set as one of "+2", "+1", "-1", and "-2",
For the selection switch,
connecting to the second voltage in the first period and to the first voltage in the second period when the value of the quantization result is "+2";
when the value of the quantization result is "+1", connecting to the reference potential in the first period and to the first voltage in the second period;
when the value of the quantization result is "-1", connecting to the reference potential in the first period and to the second voltage in the second period;
2. The D/A conversion circuit according to claim 1, wherein when the value of said quantization result is "-2", it connects to said first voltage in said first period and to said second voltage in said second period. ). A quantization result in which the quantization circuit compares the analog potential with five threshold voltages and converts the analog potential into four levels is repeatedly performed twice, and
In the first quantization, the analog potential is "2" above the positive second threshold, "1" below the second positive threshold and above the first positive threshold, below the first positive threshold and "-1" at or above the reference threshold, "1" at or above the negative first threshold and below the reference threshold, "-1" at or above the second negative threshold and below the first threshold, negative provided that it is generated as a digital value of "-2" below the second threshold;
In the second quantization, the analog potential is "2" at the positive first threshold or more, "1" at the positive reference threshold or more and less than the positive first threshold, less than the reference threshold and the negative A digital value generated as "-1" above the first threshold and "-2" below the negative first threshold and above the second negative threshold is given,
3. The D/A conversion circuit according to claim 2, wherein a 9-level digital value is generated from said quantization circuit by outputting a 4-level analog potential to said output terminal through said first period and said second period. . 3. A quantization circuit that compares an analog potential with five threshold voltages, converts the analog potential into a four-level digital value, and generates an input digital signal to be supplied to the D/A conversion circuit according to claim 2, The five threshold voltages are a reference threshold (Vth0) corresponding to the reference potential, positive and negative first thresholds (Vth1+, Vth1-) having a positive/negative first voltage difference from the reference threshold, It is set as positive and negative second thresholds (Vth2+, Vth2-) having a difference of a second voltage larger than the first voltage in positive and negative, and the input analog potential is equal to or higher than the positive second threshold. 2", "1" when less than the positive second threshold and the first positive threshold or more, "-1" when less than the positive first threshold and the reference threshold or more, less than the reference threshold and the negative first A quantization circuit that generates a digital value of "1" when it is one threshold or more, "-1" when it is less than the first negative threshold and is more than the second negative threshold, and "-2" when it is less than the second negative threshold. (4) and
a D/A conversion circuit (6) according to claim 2;
an amplifier (3) adding an analog potential input from the outside and an analog potential output from the D/A conversion circuit to obtain an analog potential to be input to the quantization circuit;
A/D conversion circuit. configured as a ΔΣ modulation type A/D conversion circuit,
5. The A/D conversion circuit according to claim 4, wherein said quantization circuit executes conversion processing at least twice in response to said externally input analog potential to generate a 9-level digital value. The quantization circuit, in the second conversion process,
The analog potential input from the outside is "2" when the positive first threshold or more, "1" when it is less than the positive first threshold and the reference threshold or more, and is less than the reference threshold and the negative first threshold. 5. The A/D conversion circuit according to claim 4, which generates a digital value of "-1" above and "-2" below the negative first threshold. The quantization circuit is
5. The A/D conversion circuit according to claim 4, wherein the positive/negative second threshold is set such that the absolute value of the difference from the reference threshold is larger than the first threshold and is an integer multiple. The quantization circuit is
5. The A/D conversion circuit according to claim 4, wherein the positive and negative second threshold is set such that the absolute value thereof is larger than the first threshold and smaller than twice the first threshold.

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