JPS58148435A - Isolated diffusion method - Google Patents
Isolated diffusion methodInfo
- Publication number
- JPS58148435A JPS58148435A JP3216382A JP3216382A JPS58148435A JP S58148435 A JPS58148435 A JP S58148435A JP 3216382 A JP3216382 A JP 3216382A JP 3216382 A JP3216382 A JP 3216382A JP S58148435 A JPS58148435 A JP S58148435A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- diamond blade
- width
- depth
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 19
- 239000010432 diamond Substances 0.000 claims abstract description 16
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 238000000926 separation method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 3
- 239000010426 asphalt Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体板内に形成される領域の間において板の
表面から裏面まで貫通し、少なくとも一方の面において
は隣接する領域と異なる導電形を有する分離領域を形成
する分離拡散方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention penetrates between regions formed in a semiconductor board from the front surface to the back surface of the board, and forms an isolation region having a conductivity type different from that of the adjacent region on at least one surface. Concerning separation and diffusion methods.
この分離領域は集積回路における隣接領域間の絶縁ある
いはこの領域において分割される、例えばプレーナ形の
各個別素子の周縁部の保匪などの役目をする。従って半
導体素子の機能には直接関与しないので半導体板面積の
有効活用のためにはその幅が必要以上に広くなることを
避けなければならない。このため第１図に示すように半
導体板１の形成すべき分離領域の中央に＃Ｉ２を予め形
成し、その後で両面よシ拡散を実施して拡散領域３を形
成することが行なわれる。このような溝２の存在によシ
拡敢領域の幅Ｗは＠２図に示すような溝のない場合の拡
散領載着の幅Ｖにくらべて狭くなシ、を九半導体板ｌを
貫通する拡散領域を形成するのに必要な拡散時間も短く
てすむ。＃Ｉ２は、例えば第３図に示すように半導体板
ｌの表面を７オトレジストあるいはアスファルトピッチ
などの層５によって覆い、この層６の一部６を化学的ま
たは機械的方法で所定のパターンに応じて除去し、次い
でエツチング液を用いて溝部２の半導体材料をエッチア
ウトする方法で形成されていた。しかしこの方法では、
エツチング条件が＄２の深さに微妙に影響し、深さの制
御が−Ｌ＜、深＜なシすぎた時は半導体板ｌの取シ扱い
の際の割れの発生が多くなシ、深さが浅すぎる時には拡
散領域３が貫通しないことがあって拡散の終点判定が！
ＡＩＩＡになる。This isolation region serves as an insulation between adjacent regions of the integrated circuit or as a protection for the periphery of each individual component, for example planar, which is divided in this region. Therefore, since it is not directly involved in the function of the semiconductor element, in order to effectively utilize the area of the semiconductor board, it is necessary to avoid making the width of the board wider than necessary. For this reason, as shown in FIG. 1, #I2 is previously formed in the center of the isolation region to be formed in the semiconductor substrate 1, and then diffusion is performed on both sides to form the diffusion region 3. Due to the presence of such a groove 2, the width W of the diffusion region is narrower than the width V of the diffusion region without the groove as shown in Figure 2. The diffusion time required to form the diffusion region is also short. In #I2, for example, as shown in FIG. 3, the surface of the semiconductor board 1 is covered with a layer 5 of photoresist or asphalt pitch, and a part 6 of this layer 6 is chemically or mechanically coated in a predetermined pattern. The semiconductor material in the trench 2 is then etched out using an etching solution. But with this method,
Etching conditions slightly affect the depth of $2, and if the depth is controlled too much -L<, depth<, there will be many cracks when handling the semiconductor board. If the depth is too shallow, the diffusion region 3 may not penetrate, making it difficult to determine the end point of diffusion!
Become AIIA.
本発明は上述の欠点を除去して所定の深さと幅を有する
溝を形成して行なうことのできる分離拡散方法を提供す
ることを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a separation and diffusion method that can eliminate the above-mentioned drawbacks and can be carried out by forming a groove having a predetermined depth and width.
この目的は半導体板の少なくとも一方の表面の分離領域
を設ける位置の中央にダイヤモンドブレードを用いて溝
を形成し、その後不純物の拡散を行なうことによって達
成される。This objective is achieved by forming a groove with a diamond blade in the center of at least one surface of the semiconductor plate at the location where the isolation region is to be provided, followed by diffusion of impurities.
以下図を引用して本発明の実施例について説明する。第
４図に示すように＃ｌＩ２は、ダイヤモンドを円板の周
縁に付着させたダイヤモンドブレードフを高速に回転さ
せながら所定のパターンに浴って切り込むことによって
形成する。＃＄２の幅はダイヤモンドブレード７の幅に
よって決まシ、溝２の深さもダイヤモンドブレードのス
トロークによシ決まるため制御容易で均一な溝をしかも
短時間で得ることができる。Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 4, #lI2 is formed by cutting a diamond blade in a predetermined pattern while rotating at high speed with a diamond blade having diamonds attached to the periphery of the disk. Since the width of #$2 is determined by the width of the diamond blade 7 and the depth of the groove 2 is also determined by the stroke of the diamond blade, uniform grooves can be easily controlled and obtained in a short time.
ダイヤモンドブレード７によって機械的に形成された＄
２の表面状態に問題があるときは、このめと＃２の深さ
１幅に大きな影響を与えない程度にエツチングすること
もできる。$ mechanically formed by diamond blade 7
If there is a problem with the surface condition of #2, etching can be done to the extent that it does not significantly affect the depth and width of #2.
以上述べたように本発明は予め溝を形成したのち拡散を
実施する分離拡散法において溝をダイヤモンドブレード
の切り込みによシ機械的に形成するものである。これに
よシ均一な幅と深さを有する溝を形成できるので半導体
板の割れが発生することなく、これを用いて狭い幅の分
離領域が短時間の拡散によって確実に形成でき、半導体
面積を有効に利用した半導体素子等の製造に対して大き
な効果を有する。As described above, in the present invention, grooves are mechanically formed by cutting with a diamond blade in a separation diffusion method in which grooves are formed in advance and then diffusion is carried out. This makes it possible to form grooves with uniform width and depth, which prevents cracking of the semiconductor board.Using this, narrow isolation regions can be reliably formed in a short time by diffusion, reducing the semiconductor area. It has a great effect on the production of semiconductor devices etc. when used effectively.
第１図は予め溝を形成して行なう分離拡散方法を示す断
面図、第２図は溝を形成しない分離拡散方法を示す断面
図、第３図は従来の溝形成法を示す断面図、第４図は本
発明の一実施例の溝形成法を示す断面図である。
１・・・半導体板、２・・・溝、フ・・・ダイヤモンド
ブレード。FIG. 1 is a cross-sectional view showing an isolation/diffusion method in which grooves are formed in advance, FIG. 2 is a cross-sectional view showing an isolation/diffusion method in which no grooves are formed, and FIG. 3 is a cross-sectional view showing a conventional groove-forming method. FIG. 4 is a sectional view showing a groove forming method according to an embodiment of the present invention. 1...Semiconductor board, 2...Groove, F...Diamond blade.
Claims (1)
る位置の中央にダイヤモンドブレードを用いて郷を形成
し、その後不純物の拡散を行なうことを特徴とする分離
拡散方法。1) A separation/diffusion method characterized in that a diamond blade is used to form a region at the center of a location where a separation region is to be provided on at least one surface of a semiconductor substrate, and then impurities are diffused.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3216382A JPS58148435A (en) | 1982-03-01 | 1982-03-01 | Isolated diffusion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3216382A JPS58148435A (en) | 1982-03-01 | 1982-03-01 | Isolated diffusion method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58148435A true JPS58148435A (en) | 1983-09-03 |
Family
ID=12351266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3216382A Pending JPS58148435A (en) | 1982-03-01 | 1982-03-01 | Isolated diffusion method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58148435A (en) |
-
1982
- 1982-03-01 JP JP3216382A patent/JPS58148435A/en active Pending
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