JPS58147719A - Camera - Google Patents

Abstract

PURPOSE:To always execute image pickup of a normal luminance level, by designating flash image pickup, or the like, in case when a signal reset time of an image pickup means exceeds a prescribed time. CONSTITUTION:If a signal integral type image pickup means IS does not reach a prescribed level after a prescribed reset time by which an overflow drain gate becomes a high level through a duty ratio controlling circuit DC has passed, an output of a recording signal generating circuit VP drops. As a result, an output of a comparator CP1 is inverted to a low level, an output of a NOR gate NG is inverted to a high level, and by lighting of an LEDLD1 trhough a transistor TR1, and an alarm by a timer TM, a sounding body SE, etc., flash image pickup is designated. In this case, automatic setting to a flash image pickup mode can be executed, too, in the same way. According to this constitution, image pickup of an exact luminance level can be executed at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a camera, particularly a signal integrating type m
The invention relates to a camera using 41 means.

For example, it is well known that the signal integration time of a C0D1BBD or MO8 image sensor can be controlled arbitrarily; In a camera that uses a camera as an imaging means, the signal integration time of the imaging means is controlled in accordance with the brightness of the object to be photographed, etc. so that it can better follow a wide range of brightness changes that may or may not be photographed. That is advantageous. In other words, if the object is bright, the integration time is controlled to be short or long, and if it is dark, the integration time is controlled to be long. If we consider the deterioration of 8/N due to the increase of

In view of such circumstances, the present invention is capable of always guaranteeing photographing at an appropriate brightness level, particularly when using a signal integration type imaging means as an imaging means, regardless of restrictions on the long side of the signal integration time. In order to ensure a predetermined level of imaging signals, the present invention provides a method for instructing photographing with a flash device when the signal integration time of an imaging flat film exceeds a predetermined time to ensure an imaging signal of a predetermined level. The second feature is that the camera is equipped with a means for automatically setting the camera to a mode for photographing using a flashlight.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, the first embodiment of the present invention will be explained with reference to FIG. 12 To explain, 1 In the same figure, a solid-state image sensor such as the above-mentioned C'CD, BBD, or MOS image sensor is used as a 1sFi signal integration type imaging means, and here, for example, the well-known overflow・It is an area type CCU with a train gate (OQ). Clock from the synchronization and control circuit 80C that controls 18DFi synchronization signal generation and sequence control.
A confectionery drive circuit drives the image sensor 1S with pulses, and P is a well-known recording circuit that processes the image sensor 18 from the image sensor 18 using a synchronization signal from the synchronization and control circuit SGC to generate a recording signal. (The i generation circuit, RC, is a recording circuit that is also controlled by the control signal of the synchronization and control circuit SGC, and the recording circuit RC controls the magnetic head IID.
As is well known, a video signal is recorded on a magnetic disk D8 which is rotationally driven by a motor MTK. still,
MCFi synchronization and control circuit 8 This is a motor control circuit that controls the rotation of the disk D80 by the motor MT using a synchronization signal from the GC. Here, in this example, 1/s
It is assumed that the reading of the photographing signal is repeated at intervals of O seconds, and therefore the signal integration time t' of the image pickup device 18 is set to be the longest and controlled within the first second.

1. When the Ml image sensor Is receives the light, it measures the elements such as N,
According to the photometric value, for example, a well-known photometric circuit that outputs a voltage signal of 8pB outputs the output voltage of the photometric circuit LM from the imaging element drive circuit llIr1SD and generates a start pulse (i.e., ν every first second). A differential circuit for reducing a predetermined voltage level V^ commensurate with the signal integration time of 1150 seconds of the imaging frame 18 from the output of the CFI core sampling circuit SP, which is a sampling circuit that samples in response to a pulse). Amplifier, DC connection is triggered by the above-mentioned readout start pulse from the element drive circuit LSD, and the connection is made according to the level of the positive output of the differential amplifier DF (ignoring the negative output) from the trigger point. This is a duty ratio control circuit that forms a pulse with a width (limited to a value less than 1/sO second), and the output of the nuclear duty ratio control circuit, which is 16DC for both times, is the overflow of the image sensor IS.・Drain/gate (OG) K is provided, and the output is I・
During the period A, the drain gate (OG) is turned on, and during this period, the signal (charge) generated in the imaging section is not accumulated and overflows through the overflow drain gate (OG). - The signal integration time of the image sensor Is is (first second) - (overflow〇 Drain gate OG ON period →
It is controlled as the output of the duty ratio control circuit DC) and the ino period).

The CPI compares the III-degree signal Y generated by the recording signal generation circuit vP with the reference level Ve, which is the basis for guaranteeing the 2f$ signal at a predetermined level, and determines whether the level of the good signal Y is this level. When the level of the image pickup signal from the image pickup device 1S falls below the reference level Va, in other words, when the level of the image pickup signal from the image pickup element IS has decreased to such a level that the recording signal at the predetermined level cannot be guaranteed.
E A comparator that outputs two signals, CPsFi A comparator that outputs a low signal when the output of the differential amplifier DF becomes negative, N both Gt! A NOR gate, TR, which outputs a high signal when the outputs of the % comparators CP* and CPs are both low.
I is an npn switching transistor that responds to the output of the NOR gate NO, LDxtj is a display light emitting element connected to its collector side, and TM is a NPN switching transistor that responds to the output of the NOR gate NO. , a timer circuit that outputs a high signal, and 5FID#i a sounding element drive circuit (for example, an oscillation circuit) that drives the sounding element SE during the high output period of the timer circuit TM. Note that R1 and Rs are logging resistances.

Now, suppose that the output of the differential amplifier DF becomes negative, and therefore 1. ! The overflow drain (OG) of the image sensor Is remains off, and in the end, the signal integration time of the image sensor IS is controlled to the longest 1/60th integration time. It means that. On the other hand, as mentioned above, the low output of the comparator CPI means that the level of the imaging signal is insufficient, so the high output of the NG (noah goo) cannot guarantee proper recording. This means that the brightness of the object has decreased, and in such a case, the light emitting element LD1 emits light, and the growth element 8g grows for several seconds to provide an appropriate level of imaging signal as a flash time. If a situation arises in which a longer signal integration time is required to obtain a larger signal (assuming, of course, that it has already been set to the maximum aperture in case of an error), the light emitting element This means that a warning is issued by the IJ) 1 and the development element 8B to prompt the photographer to take a picture using the flash device F.

Now, in the above embodiment, the display is limited to a warning to encourage photography using a flash device, but it can go further, for example, in the case of a camera with a built-in flash device.

It is also possible to automatically set the camera to a flash photography mode, such as by automatically starting the flash mode. This will be explained with reference to Figure 2. In the figure, the PS company power supply circuit, 'IBs Id nPn switching transistor T
pnp switching e transistor that turns on when Rs turns on % IJ) s lj the transistor TR
The display light emitting element Fl, q is turned on by being supplied with power from the power supply circuit P8 when transistor s is turned on, and charging is started by being supplied with power from the t source circuit P8 when the transistor TRm is turned on. A flash device recommended by the camera, NE is a neon fist rung to indicate the completion of charging of its main capacitor ~, FF1j or goo) OG
The power up clear signal (PUC) is reset by the light emission completion signal from the flash device FL, while the high signal from NG in Figure 1 causes the power up clear signal (PUC) to be reset. 8 - Frigg, who was made to be
In the flop, the transistor TRs is connected to be turned on by the high Q output of the flip-flop FF. Rs, R4.

All losses are protective resistance.

According to this configuration, when the output of the Noah gate NG becomes high as described above, this triggers and starts supplying power to the flash device Fl, so that the camera automatically switches to the mode for shooting using the flash device. This will be the building that will be set. In this case, the light emitting element L) emits light to indicate that the camera has been automatically set to the flash photography mode. In this state, when the charging of the main capacitor in the flash device [FL is completed, the neon lamp NB lights up.For example, the aperture aperture of the aperture device (not shown) can be changed to the specified aperture value of the flash device by the charging completion signal at this time. If you have a model that automatically adjusts to the
'i It is also possible to automatically operate the forceps-diaphragm interlocking mechanism. In addition, in a fully charged state, the flash device [FL trigger 4] emits light within the signal accumulation period in the sensor 18 through the synchronization and control circuit 8GC in response to a command from a release (not shown), for example. It is necessary to make sure that the trigger is applied in the same way. flash device p
When the light emission of L is completed, 7 lip 7a Tsug FF! When the voltage is turned off and the transistors TRs and TRs are turned off, the power supply to the flash device PL is cut off.

In addition to this, for example, as shown in Figure 3, in cameras that have a built-in pop/7-pop type flash device, the Noah
You may use IJK to automatically set the camera to flash photography mode by automatically pop-up the flash device using the high output of NG). That is, in the same figure, the flash device FLa, the bottle Pl on the camera body side, and the device 1! The switch pin 8WPPc latch lever LL latches against the pop-up spring P8F stretched between the pin L and the bottle P1 at the position shown in i, where it is pushed into the camera. When engaged under the action of spring 1.SP, it is held in place.In addition, the rotation axis of ^xFi latch 9 lever LL, RP#f rotation restriction pin TR number is shown in Fig. 1 (Noah Goo) NG The npn switching transistor MG is turned on by the high output of NOR gate NG, and MG is a magnet that is energized by turning on the transistor T. That is, when the magnet MGIC is energized by the high output of the NOR gate NG, The double lever LL is rotated counterclockwise about the axis AX against the spring L8P, and at this time releases the latch of the switch pin SWP.This causes the flash device FL to move under the action of the spring P8P. Pop it up until the stop bottle 8TP collides with the stopper ST on the camera body side and is regulated.
In this position, switch bin 8WP is switched to switch S.
Close W. By using the switch SW in place of, for example, the transistor T- in FIG. 2, it is possible to start supplying power to the flash device PL as described above by closing the switch SW.

Next, another embodiment of the present invention will be described with reference to FIG. This embodiment eliminates the limit on how long the signal integration time of the image sensor LS can be, theoretically allowing it to be made as long as desired, while making it possible for the signal integration time to exceed a predetermined time. In this case, an announcement is made to encourage photography using a single flash device, or automatic setting is made to the flash photography mode.

In FIG. 4, the same reference numerals as in FIG. 1 indicate the same elements as already described. In the figure, when the integrated signal amount in any pixel of an image sensor 181i reaches a predetermined amount K (specific KFi, for example, a value that can guarantee an appropriate level of image pickup signal for the entire pixel), the terminal It is configured so that a high signal can be output from the OD. Specifically, such a structure may be one with a well-known overflow train. Furthermore, the image pickup element drive circuit 18D is configured to read an image pickup signal from the element IS in response to a high output from the terminal OD of the image pickup element IS. Further, in order to record both image signals in accordance with the reading of the image signal from the image sensor 18, the readout start pulse from the drive circuit 18D is applied to the synchronization and control circuit SGC. D
Lt;J A delay circuit that delays the read start pulse from the drive circuit lSD by a predetermined minute time; O8#'i High level information having a predetermined duration when triggered by the output of the delay circuit DL; One output
Schott circuit (monostable multi-vibrator), LCF
D-latch circuit which receives the output of i# one-shot circuit O8 at 70D input and is configured to be triggered by a signal from terminal OD of image sensor Is, tv#ii latch circuit 1. This is an inverter that inverts the output of C.

In such a configuration, when the readout start pulse is output from the image sensor drive circuit 18D and the readout of the image signal from the image sensor Is is started, the image sensor starts capturing the next image in parallel. At this time, the one φ shot circuit O8 is triggered after a predetermined minute delay time by the delay circuit DL from the generation of the above-mentioned readout start pulse, and the signal is stored for a predetermined time. Perform level output. Here, while the output of the one-shot circuit O8 is high, if a high signal is output from the terminal OD of the image sensor lS and reading of the image signal is started, at this time, the latch circuit C causes the high signal to be output. is latched and the output of the inverter l is not output, and after the output of the one-shot circuit 08 changes to low, a high signal is output from the terminal OD. Since a low signal is output, the output of the inverter IV becomes high when the output of the inverter IV exceeds a predetermined time including the high period of the output of the high shot circuit O8. Therefore, the state power of the inverter I is applied to the base of the transistor T and the timer circuit TM in FIG.
The same effect as in the above-mentioned example can be obtained by adding the same effect to the transistor TR4 shown in FIG. 6.

Finally, another εJ according to the present invention is determined as Ff5? according to FIG.
I will clarify. This embodiment differs somewhat in that, whereas the embodiment shown in FIG. 4 controls the signal integration time in real time, it is controlled in non-real time.

That is, in FIG. 5, the same reference numerals as in FIGS. 1 and 4 are the same as described above. WP is a recording signal generation circuit v
Based on the output of the 1TcFill window comparator WP, which compares the level of the brightness signal Y from P with a predetermined voltage range K (having upper and lower limits), the brightness signal Y
The signal integration time remains unchanged when the level is within the predetermined voltage range, and the signal integration time is set to a shorter time when it exceeds the upper limit, and a longer time when it is below the lower limit. The drive circuit 18Dtj functions to control the signal integration time of the image sensor Is based on the time conveyed by the setting circuit ITC.

l T l) is a time discrimination circuit that discriminates whether the signal integration time set by the setting circuit ITC is longer than a predetermined time and outputs a high signal if it is longer, as can be understood from the above configuration. , the output amII of the time discrimination circuit lTD
! The output of the NOR gate NG shown in No. 3 can be used in the same way as the output of the inverter IV shown in FIG.

As described in detail above, according to the present invention, the lf! # In addition, it is now possible to always guarantee photography at an appropriate brightness level regardless of the restriction on the long open side of the signal integration time of the skeleton photography means.
This enables error-free photography and is extremely useful for this type of camera.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram of one embodiment of the present invention; Fig. 2 is a partial block circuit diagram showing another output form of the first embodiment; Fig. 3 is a block circuit diagram showing another output form of the first embodiment; FIG. 4 is a block circuit diagram of another embodiment of the present invention, and FIG. 5 is a block 101 circuit diagram of still another embodiment of the present invention. l S@@*@@ Signal integration type imaging means, VP, RC, H
D.MT. MC... Recording system components, DS.0... Magnetic disk, 8GC... Synchronization and control circuit, LM, 8
P, D.F. DC: lSD; WP, ITc, 18D, ... Components of signal integration time control system, CPt, CPs,
NG; DL, 08. L.C., IV. TTD, . . . Components of control means for flash photography instruction or automatic setting, LDl, SE . . . Display means,
FL・00 flash device, TRI, TRI, FF; TR4,
MG @+1@@41 Flash photography preparation means. Patented wheat Canon Co., Ltd.

Claims (1)

[Scope of Claims] A camera using a signal integration type imaging means as an imaging means, comprising a signal integration control means for controlling signal integration by the imaging means, and the imaging means for guaranteeing an imaging signal of a predetermined level. 1. A camera comprising means for automatically setting a mode for instructing photography using a flash device or a mode for photographing using a flash device when the signal integration time exceeds a predetermined time.