JPS58147240A - Phase locked oscillator - Google Patents
Phase locked oscillatorInfo
- Publication number
- JPS58147240A JPS58147240A JP57030328A JP3032882A JPS58147240A JP S58147240 A JPS58147240 A JP S58147240A JP 57030328 A JP57030328 A JP 57030328A JP 3032882 A JP3032882 A JP 3032882A JP S58147240 A JPS58147240 A JP S58147240A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- phase
- output
- dividing
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は電圧制御発振器の鉛振拘波数が基準入力信号の
贅数倍とならない位相同期発振器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked oscillator in which the vertical vibrational constant of the voltage controlled oscillator is not a multiple of a reference input signal.
一般に、位相同期発振器は、第１図に示すように、端子
７を介して与えられる基準入力信号を周波数変換回路１
によシ周波数震換した信号とこの信号の周波数に叫しく
なるよう電圧制御発振器４の出力を周波数変換回路５に
よりＪ＠波数変換した信号とを位相比較器２に与え、位
相比較を行なっ友結釆の信号から不用な高周波成分をフ
ィルタ３により除去し、この高周波成分を除去した信号
によシ１圧制御発振＆４を制御することにより基準入力
信号に位相同期した信号を出力する◇従来、このような
構成の位相同期発振器において、発振器４の出力信号の
周波数が基準入力信号の周波数の贅数倍とならないとき
には、周波数変換回路１およびＳｔｉ分周回路お上びて
い倍回路で構成されるか、または、分局比を外部から制
御できる第１の分周回路とこの第１の分周回路の分局比
を周期的に変化させるだめの第２の分周回路とを用い、
時間邑りの出力パルスの数が基準入力信号のパルス数と
等しくなるような非等周期分周回路によシ構成されてい
る。Generally, as shown in FIG.
A signal obtained by converting the frequency of the signal and a signal obtained by converting the output of the voltage controlled oscillator 4 by the frequency conversion circuit 5 to the frequency conversion circuit 5 are given to the phase comparator 2, and the phase comparison is performed. Filter 3 removes unnecessary high frequency components from the signal of the connection, and outputs a signal phase-synchronized with the reference input signal by controlling 1 pressure control oscillation & 4 using the signal from which this high frequency component has been removed.◇Conventionally, In a phase-locked oscillator with such a configuration, when the frequency of the output signal of the oscillator 4 is not a multiple of the frequency of the reference input signal, the frequency conversion circuit 1, the STI frequency divider circuit, and the STI frequency divider circuit are configured. Or, by using a first frequency divider circuit whose division ratio can be controlled from the outside and a second frequency divider circuit whose division ratio can be periodically changed,
It is constituted by an asymmetric frequency divider circuit such that the number of output pulses per time is equal to the number of pulses of the reference input signal.
しかしながら、前者の構成では、任意のてい倍器は実埃
が極めて難しく構成が複雑で素子数が多くなるうえコイ
ルおよびコンデンサー等の素子を必要とするためＩＣ（
集積回路）として一体化しにくい等の欠点がある。However, in the former configuration, it is extremely difficult for any multiplier to handle actual dust, and the configuration is complicated and requires a large number of elements, as well as elements such as coils and capacitors.
It has drawbacks such as being difficult to integrate as an integrated circuit (integrated circuit).
路により得られる出力信号には非常に大きな不用付相変
１がＸ＊されるため、所望の位相同期発振器の特性に著
しい制約をあたえる欠点がある。また、出力信号の不用
な位相変動を小さくするためには、前記第１の分周回路
の分周比を極めて初雑な周期性をもたせて変化させる必
要があり、そのためには前記第２の分周回路の分周比を
本変化させる必要が生じ、第２の分周回路の分周比を周
期的に変化させる第３．第４・・・・・・の分周回路が
必要となる等、一般に、非常に被雑な回路構成となる欠
点がある。さらに、入力信号または出力信号の周波数の
わずかな変史要求に対しても、上記の複雑な回路構成を
全く作り直はなければならない。Since the output signal obtained by the path is subjected to a very large unnecessary phase change 1, X*, there is a drawback that it severely limits the characteristics of the desired phase-locked oscillator. In addition, in order to reduce unnecessary phase fluctuations of the output signal, it is necessary to change the frequency division ratio of the first frequency divider circuit with extremely rough periodicity. It becomes necessary to change the frequency division ratio of the frequency divider circuit, and the third frequency division ratio of the second frequency divider circuit is changed periodically. Generally, there is a drawback that the circuit configuration is extremely complicated, such as the need for a fourth frequency dividing circuit. Furthermore, the above-mentioned complex circuit configuration must be completely reworked even for a slight variation in the frequency of the input signal or the output signal.
例えば、基準入力信号の周波数を５１２（Ｈ２）、電圧
制御発線番の出力信号の周波数を６３１２（ＨＥ）とし
、位相比較を５１２（Ｈｚ）で行う場合について考える
。この場合基準入力信号の周波数の７８９／６４倍が出
力信号の周波数と等しい。For example, consider a case where the frequency of the reference input signal is 512 (H2), the frequency of the output signal of the voltage control line number is 6312 (HE), and the phase comparison is performed at 512 (Hz). In this case, 789/64 times the frequency of the reference input signal is equal to the frequency of the output signal.
したがって、基準入力信号はこのまま位相比較器に入力
すればよい。一方、１゛圧制御発振益の出力信号は、１
２分周を４３回行ない１３分周を２１回行なう分周回路
に与えられ、これによシフ８９個のパルスが非等周期パ
ルスとして位相比較器に与えられる。前記分周回路は、
第１の分周回路を１２または１３分周に切換可能な分周
回路と、この第１の分周（ロ）路の出力全６４分周する
第２の分周回路とを備え、６４回のうちの初めの４３回
の間は第１の分周回路を１２分周回路として動作させ、
残りの２１回は１３分周（ロ）路として動作するよう制
御される。しかしながら、このようにして得られた出力
信号には、大きな位相変動があシ、通常、位相比較信号
としては不適当である。また、位相同期発振器の特性に
も大きな制約を与えてしまう。Therefore, the reference input signal may be input as is to the phase comparator. On the other hand, the output signal of 1゛pressure controlled oscillation gain is 1
The signal is applied to a frequency divider circuit that performs frequency division by 2 43 times and frequency division by 13 21 times, and thereby 89 shifted pulses are applied to the phase comparator as non-uniform periodic pulses. The frequency dividing circuit is
It is equipped with a frequency dividing circuit that can switch the first frequency dividing circuit to 12 or 13 frequency division, and a second frequency dividing circuit that divides the entire output of this first frequency dividing (b) path by 64 times. During the first 43 times, the first frequency divider circuit is operated as a 12 frequency divider circuit,
The remaining 21 times are controlled to operate as a 13 frequency division (b) path. However, the output signal obtained in this way has large phase fluctuations and is usually unsuitable as a phase comparison signal. Moreover, this imposes a large restriction on the characteristics of the phase-locked oscillator.
位相変動を小さくするためには、できるだけ均郷に１２
分周と１３分周とを繰返す必要がある。In order to reduce the phase fluctuation, it is necessary to
It is necessary to repeat frequency division and frequency division by 13.
均轡に近い制御の一例として、１２分周を２回繰返した
あと１３分周を１（ロ）行なうという繰返しパターンを
２０回行い、２１回目は１２分周を３回繰返したあと１
３分周を１回行うという方法があり、これによると、１
２分周と１３分周とがほぼ均尋に近く配分され位相変動
が小さくなる。As an example of control that is close to uniformity, a repeating pattern of dividing by 12 twice and then dividing by 13 by 1 (b) is performed 20 times, and on the 21st time, dividing by 12 is repeated 3 times and then by 1.
There is a method of dividing the frequency by 3 once, and according to this method, 1
The frequency division by 2 and the frequency division by 13 are distributed almost evenly, and the phase fluctuation is reduced.
すなわち、数式に書くと、（１）式のようにめられせる
。In other words, when written in a mathematical formula, it is expressed as equation (1).
（（１２Ｘ２＋１３Ｘ１）Ｘ２０＋（１２Ｘ３＋１３）
ＸＩ ）＝７８９ ・・・・・・・
・・・・・・・・ （１）このような制御を行うために
は、第２の分周回路として３分周または４分周に切換可
能な分周回路とこの第２の分周回路を制御する２１分周
を行う第３の分周回路とが必要となる。本例の場合、位
相比較周波数を入力信号の周波数５１２（Ｈ２）と出力
信号周波数６３１２（Ｈｚ）との最大公約数である８（
Ｈｌ）とし、この周波数で位相比ｋＴｈ行うとすれは分
周カウンタは等分周カウンタになり簡単になるが、位相
同期発振器の利得が非常に低下し、定常位相談差が大き
くなシ、出力信号の位相の変動範囲が広がってしまい応
答にも時間１喪す。((12X2+13X1)X20+(12X3+13)
XI)=789 ・・・・・・・・・
(1) In order to perform such control, a frequency dividing circuit that can be switched to 3 or 4 frequency division as a second frequency dividing circuit, and this second frequency dividing circuit are required. A third frequency dividing circuit that performs frequency division by 21 is required. In this example, the phase comparison frequency is set to 8 (the greatest common divisor of the input signal frequency 512 (H2) and the output signal frequency 6312 (Hz).
Hl), and if the phase ratio kTh is performed at this frequency, the frequency division counter becomes an equal frequency division counter and becomes simple, but the gain of the phase synchronized oscillator is extremely reduced, and the steady state difference is large. The fluctuation range of the signal phase is expanded, and response time is also lost.
このように、従来の位相同期発振器は、回路構成が複雑
で、特殊な分周器を必要とし、また、入力周波数と出力
周波数との最大公約数まで分周して位相比較を行なった
ときには位相比較周波数が低下してしまい位相同期発振
器の出力位相の不確実な領域が広がってし−まう等の欠
点がある。In this way, conventional phase-locked oscillators have complex circuit configurations and require special frequency dividers, and when phase comparison is performed after dividing to the greatest common divisor of the input frequency and output frequency, the phase There are disadvantages such as the comparison frequency is lowered and the uncertain region of the output phase of the phase synchronized oscillator is widened.
本発明の目的は上述の欠点を除去した位相同期発振器を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked oscillator which eliminates the above-mentioned drawbacks.
本発明の位相同期発振器Ｉ／ｉ％電圧制御発振手段と、
核発振十段の出力信号を分周する第１０分周手段と、該
第１０分周手段の出力信号を分周するＭ２の分周手段と
、該第２の分局手段の出力信号によシアドレス選択され
この選択されたアドレスの内容に応じて前ｓｒ：、第１
の分局手段の分局比を制御する記憶手段と、前記第１０
分周手段の出力信号と入力信号または第３０分周手段を
介して分周された入力信号との位相を比較しこの比較結
果により前記発振手段の発振周波数を制御する位相比較
手段とから構成されている。Phase synchronized oscillator I/i% voltage controlled oscillation means of the present invention,
A tenth frequency dividing means for frequency dividing the output signal of the ten stages of nuclear oscillation, an M2 frequency dividing means for frequency dividing the output signal of the tenth frequency dividing means, and an output signal of the second division means. The address is selected and according to the contents of this selected address the previous sr:, the first
storage means for controlling the division ratio of the division means;
and a phase comparing means for comparing the phase of the output signal of the frequency dividing means and the input signal or the input signal frequency-divided via the 30th frequency dividing means, and controlling the oscillation frequency of the oscillating means based on the comparison result. ing.
次に本発明について図面を参樒して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.
第２図は本発明の一実施例を示すプロ、り図であシ、参
照数￥２０は基準信号入力端子、同数字パスフィルタ、
同数字１２は霜圧制＠発振器、同数字３０は出力端子で
ある。同数字１３は１°圧制御発振器１２の出力信号を
分周する第１の分周回路であり、分局比はプリセット入
力端子Ａ ｏ −ｋ ｎに与えられる固定記憶回路１５
の並列出力信号４１によシ制御される。同数字１４は第
１の分周回路１３の出力を分周する第２の分周回路でめ
り、その並列出力信号４０は固定記憶回路１５のアドレ
ス入力部に与えられている。Figure 2 is a professional diagram showing an embodiment of the present invention.
The number 12 is the frost suppression@oscillator, and the number 30 is the output terminal. The same number 13 is a first frequency dividing circuit that divides the output signal of the 1° pressure controlled oscillator 12, and the division ratio is given to the preset input terminal Ao-kn of the fixed memory circuit 15.
It is controlled by the parallel output signal 41 of . The same number 14 is generated by a second frequency dividing circuit which divides the output of the first frequency dividing circuit 13, and its parallel output signal 40 is applied to the address input section of the fixed storage circuit 15.
次に動作について説明する。Next, the operation will be explained.
端子２０から与えられる基準入力信号の周波数を５１２
（ＨＥ）、端子３０に出力される出力信号のＮ＠波数を
６３１２（Ｈｚ）とし、位相比較は５１２（Ｈｚ）でｂ
うものとする。分周回路１３の出力は分周回路１４に与
えられるとともに自分自身のロード（ＬＯＡＤ）端子１
６にも与えられこれに応答してスタート位相を決定する
と、ドパターンを固定記憶回路１５から取り込む。The frequency of the reference input signal given from the terminal 20 is set to 512
(HE), the N@ wave number of the output signal output to terminal 30 is 6312 (Hz), and the phase comparison is 512 (Hz).
And Umono. The output of the frequency dividing circuit 13 is given to the frequency dividing circuit 14 and its own load (LOAD) terminal 1.
6, and in response to this, the start phase is determined and the dot pattern is taken in from the fixed storage circuit 15.
分周回路１４は分周回路１３の出力を６４分周しており
、その出力信号４０が固定記憶回路１５のアドレスを選
択している。固定記憶回路１５の内容は、例えば、４Ｘ
６４ビツトのデータすなわち６４個の４ビ、トデータが
各記憶場所に格納されておシ、その格納順に従って分周
回路１３の分周比が決定される。The frequency dividing circuit 14 divides the output of the frequency dividing circuit 13 by 64, and its output signal 40 selects the address of the fixed storage circuit 15. The contents of the fixed memory circuit 15 are, for example, 4X
64-bit data, ie, 64 pieces of 4-bit data, are stored in each storage location, and the frequency division ratio of the frequency divider circuit 13 is determined according to the order in which they are stored.
例えは、分周回路１３を４と、トのバイナリア、プカウ
ンタにより構成し４ビツト全てが−２のときキャリイ信
号端子１７からキャリイ信号が出るとすると、この信号
が出たときに固定記憶回路１５からビットパターン’０
０１１’を取り込みこれをセットすれはこの分周回路１
３は１３分周回路として動作し、同様にキャリイ信号が
出たときに’０１００’をセットすれば１２分周回路と
して動作する。したがって、１２分周および１３分周を
行なわせたい順に、ビットパターン’０１００’および
”００１１’をそれぞれ記憶回路に予め記憶させてお次
に、入力端子２０と位相比較器１１との間にＮ分周回路
を挿入したときの動作について説明する０
基準入力信号周波数ｆ、と出力信号周波ａｆｔとの周波
数比をＦ、／Ｆ、（ただし既約分数）とする。このとき
、分周回路１３および分周回路１４の分周回数は以下の
規則によシ決定される。For example, if the frequency divider circuit 13 is configured with a binary ap counter of 4 and from bit pattern '0
Take in 011' and set it to this frequency divider circuit 1.
3 operates as a frequency divider by 13 circuit, and similarly, if '0100' is set when a carry signal is output, it operates as a frequency divider by 12 circuit. Therefore, bit patterns '0100' and '0011' are stored in advance in the storage circuit in the order in which frequency division by 12 and frequency division by 13 are desired, respectively, and then N The operation when a frequency divider circuit is inserted is explained.0 Let the frequency ratio between the reference input signal frequency f and the output signal frequency aft be F, /F (an irreducible fraction).In this case, the frequency divider circuit 13 The frequency division number of the frequency dividing circuit 14 is determined according to the following rules.
分周回路１３は１／Ｍまたは１／（Ｍ＋１）を分局比と
して選択可能な分周回路とする（ただしＭはＮＸＦ、／
Ｆ１を越えない最大の整数）。分周回路１４は１／ＦＮ
を分周比とする分周回路とする。（たたし、ＦＮはＮと
Ｆ、の最／ＪＳ公倍数とする）。分周回路１３０Ｍおよ
び（Ｍ＋１）分局の回数はＭ分周の回数をｘ、（Ｍ＋１
）分周の回数をｙとすれは、下記の連立方程式を満たす
値をとれはよい。The frequency dividing circuit 13 is a frequency dividing circuit that can select 1/M or 1/(M+1) as the division ratio (M is NXF, /
(largest integer not exceeding F1). The frequency dividing circuit 14 is 1/FN
Assume that the frequency dividing circuit has a dividing ratio of . (However, FN is the highest common multiple of N and F.) The frequency dividing circuit 130M and the number of (M+1) divisions are calculated by multiplying the number of times of M frequency division by x, (M+1)
) Let y be the number of frequency divisions, so long as it takes a value that satisfies the following simultaneous equations.
ｘ＋ｙ ＝ＦＮ ・・・・・・・・・
（３）このときの固定記憶回路の容量はＫＸＦＮビット
分必髪となる。ただし、Ｋは分周回路１３０プリセ、ト
に必要など、ト数である。x+y=FN ・・・・・・・・・
(3) At this time, the capacity of the fixed storage circuit must be equal to KXFN bits. However, K is the number of times required for the frequency dividing circuit 130.
式（２）および（３）を満たすＸおよびｙは必ず存在す
る。すなわち、両式をｙについて解くと、るから、（４
）式の右辺は正となる。また、ＦＮはＦｌとなる。X and y that satisfy formulas (2) and (3) always exist. That is, if we solve both equations for y, we get (4
) is positive. Further, FN becomes Fl.
したがって、ｙは正の整数となる。同様にＸは、ｘ＝ｆ
’Ｎ（１＋Ｍ −Ｆ、／Ｆ１） ・・・・・・・・・
（５）であるから、ｙと同じ理山によシ必ず正の整数と
なる。Therefore, y is a positive integer. Similarly, X is x=f
'N(1+M -F, /F1) ・・・・・・・・・
(5), so by the same logic as y, it is always a positive integer.
このように１分周回路１３の分周比１／Ｍおよび１／（
Ｍ＋１）ならひにこれらの動作回数Ｘおよびｙ１分周回
路１４の分周比１／ＦＮを設定することにより、位相比
軟周期を一致させるための非等周期分周回路１８が構成
できる。In this way, the frequency division ratios of the 1 frequency divider 13 are 1/M and 1/(
M+1), by setting the number of operations X and the frequency division ratio 1/FN of the y1 frequency divider circuit 14, an asymmetric frequency divider circuit 18 for matching the phase ratio soft cycles can be constructed.
＃！３図は本発明の他の実施例を示すプロ、り図であり
、第２１において帰還ループに設けてぃたの間に接続し
、帰還ルーズには通為の分周回路１９を設けである。#! Fig. 3 is a diagram showing another embodiment of the present invention, in which the feedback loop is connected in the 21st section, and a regular frequency dividing circuit 19 is provided in the feedback loop. .
ｖ上、本発明には、簡単な（ロ）路構成によシどのよう
な被雑な非郷分分配で８実埃出米るので、入出力周波数
が整数倍の関係にない位相Ｎ期発振器において、位相比
較周波数を人、出力板波数の最大公約数よシ高くでき、
出力の位相ｗ４差が小さく、また、不用位相震Ｉ！７＋
が最Ｉトとなシ、応答％性が速くなる郷の位相同期発振
器の特性上の制約を大きく数置できるという効果がある
。v. On the other hand, in the present invention, a simple (b) path configuration will result in 8 real problems with any kind of complicated non-local distribution. In the oscillator, the phase comparison frequency can be made higher than the greatest common divisor of the output plate wave number,
The output phase w4 difference is small, and the unnecessary phase tremor I! 7+
The most important advantage is that the characteristic constraints of the phase-locked oscillator can be greatly reduced, which increases the response rate.
また、入力または出力の周波数が多少変更されても固定
記憶回路の内容を変更するのみで回路構成を変更する必
要がないため汎用性が高（ＩＣ化も容易である。さらに
、固定記憶回路は、分周回路１４でアドレス選択される
ので、電圧制御発振器の出力が高い周波数であっても低
速動作でよい。In addition, even if the input or output frequency changes slightly, it is only necessary to change the contents of the fixed memory circuit and there is no need to change the circuit configuration, so it is highly versatile (can be easily integrated into an IC. , the addresses are selected by the frequency divider circuit 14, so even if the output of the voltage controlled oscillator has a high frequency, low speed operation is sufficient.
第１図は従来の位相同期発振器を示すプロ、り図におい
て、１，５，１０，１３，１４．１９・・・・・・分周
回路、２．１０・・・・・・位相比較器、３．１１・・
・・・・ローパスフィルタ、４．１２・・・・・・電圧
制御発振器、１５・・・・・・固定記憶回路、 ７ 、
８．２０．３０・・・・・・端子、１６・・・・・・ロ
ード端子、１７・・・・・・キャリイ信号端子、１８・
・・・・・非等周期分周（ロ）路。
第１閏
第２閲
ｔ
第３閉
−２：Figure 1 shows a conventional phase-locked oscillator; , 3.11...
...Low pass filter, 4.12...Voltage controlled oscillator, 15...Fixed memory circuit, 7,
8.20.30...Terminal, 16...Load terminal, 17...Carry signal terminal, 18.
...A non-equal period dividing (b) path. 1st Leap 2nd View 3rd Close-2:
Claims (2)
を分周する第１の分局手段と、該第１の分局手段の出力
信号を分周する第２の分局手段と、骸＃！２の分局手段
の出力信号によりアドレス選択されこの選択されたアド
レスの内容に応じて前記第１の分局手段の分周比を制御
する記憶手段と、前記第１０分周手段の出力信号と入力
信号または第３の分周手段を介して分周された入力信号
との位相を比較しこの比較結果によシ前記発振手段の発
振周波数を制御する位相比較手段とから摘成さｔたこと
金特歓とする位相同期発振器。(1) A voltage controlled oscillation means, a first division means for frequency dividing the output signal of the oscillation means, a second division means for dividing the frequency of the output signal of the first division means, and Mukuro #! storage means for selecting an address by the output signal of the second dividing means and controlling the frequency division ratio of the first dividing means according to the contents of the selected address; and the output signal and input signal of the tenth dividing means. or phase comparison means for comparing the phase with the input signal frequency-divided via the third frequency dividing means and controlling the oscillation frequency of the oscillation means based on the comparison result. This is a phase-locked oscillator.
を分周する第１の分局手段と、入力信号を分周する第２
の分局手段と、該第２０分周手段の出力信号を分周する
第３の分局手段と、該第３の分局手段の出力によシアド
レス選択されこの選択されたアドレスの内容に応じて前
記第２の分段の出力信号との位相を比較しこの比較結果
により前記発振手段の発振胸波数を制御する位相比較手
段とから構成されたことを％像とする位相同期発振器。(2) A pressure-controlled oscillation means, a first division means for frequency-dividing the output signal of the oscillation means, and a second division means for frequency-dividing the input signal.
a third division means for frequency-dividing the output signal of the 20th frequency division means; a sea address is selected by the output of the third division means; and a phase comparison means for comparing the phase with the output signal of the second division stage and controlling the oscillation chest wave number of the oscillation means based on the comparison result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57030328A JPS58147240A (en) | 1982-02-26 | 1982-02-26 | Phase locked oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57030328A JPS58147240A (en) | 1982-02-26 | 1982-02-26 | Phase locked oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58147240A true JPS58147240A (en) | 1983-09-02 |
Family
ID=12300736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57030328A Pending JPS58147240A (en) | 1982-02-26 | 1982-02-26 | Phase locked oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147240A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS545319A (en) * | 1977-06-15 | 1979-01-16 | Hitachi Ltd | Transceiver of multi-channel |
| JPS5425658A (en) * | 1977-07-28 | 1979-02-26 | Matsushita Electric Ind Co Ltd | Prequency demultiplier |
| JPS54128253A (en) * | 1978-03-29 | 1979-10-04 | Anritsu Electric Co Ltd | Frequency synthesizing circuit |
| JPS5518829B2 (en) * | 1977-04-13 | 1980-05-21 |
-
1982
- 1982-02-26 JP JP57030328A patent/JPS58147240A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5518829B2 (en) * | 1977-04-13 | 1980-05-21 | ||
| JPS545319A (en) * | 1977-06-15 | 1979-01-16 | Hitachi Ltd | Transceiver of multi-channel |
| JPS5425658A (en) * | 1977-07-28 | 1979-02-26 | Matsushita Electric Ind Co Ltd | Prequency demultiplier |
| JPS54128253A (en) * | 1978-03-29 | 1979-10-04 | Anritsu Electric Co Ltd | Frequency synthesizing circuit |
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