JPS58147049A - Semiconductor stack - Google Patents
Semiconductor stackInfo
- Publication number
- JPS58147049A JPS58147049A JP2856282A JP2856282A JPS58147049A JP S58147049 A JPS58147049 A JP S58147049A JP 2856282 A JP2856282 A JP 2856282A JP 2856282 A JP2856282 A JP 2856282A JP S58147049 A JPS58147049 A JP S58147049A
- Authority
- JP
- Japan
- Prior art keywords
- bolt
- hollow
- semiconductor stack
- fin
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/44—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements the complete device being wholly immersed in a fluid other than air
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体スタック、特に複数個のスタッド形半導
体素子に冷却フィンを複数個組み合せた構成に於いて、
温度分布の均−化並びに小型、軽量化の上で好適な半導
体スタックに関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor stack, particularly in a structure in which a plurality of stud-shaped semiconductor elements are combined with a plurality of cooling fins.
The present invention relates to a semiconductor stack suitable for uniform temperature distribution, size, and weight reduction.
〔発明の技術的背景コ
第1図及び第2図は周知の半導体スタックの構造を示す
平面図及び正面□□□で、特にスタッド形半導体素子を
複数個並列にして使用する場合t−例示するものである
。つまり、111図、@2因に示した半導体スタックは
スタッド形半導体素子lを冷却フィン2に取付けて菓子
ユニットを411成し、各冷却フィン2に設けられた穴
3にボルト4を貫通して締付けることによって、各冷却
フィン2を互いに連結して構成されるものである。[Technical Background of the Invention] Figures 1 and 2 are a plan view and a front view showing the structure of a well-known semiconductor stack, particularly when using a plurality of stud-shaped semiconductor elements in parallel. It is something. In other words, the semiconductor stack shown in Figure 111 @2 causes a confectionery unit 411 by attaching a stud-shaped semiconductor element l to a cooling fin 2, and inserting a bolt 4 through a hole 3 provided in each cooling fin 2. The cooling fins 2 are connected to each other by tightening.
ちなみに、従来の半導体スタックに於いてtよ、冷却フ
ィン2を連結するためのボルト4に第3図の儒面図に示
す如く、ソリッF411造、つまり中空部のない構造の
ものを用いていたため、以下に述べる様な問題点があっ
た。By the way, in conventional semiconductor stacks, the bolts 4 for connecting the cooling fins 2 were made of solid F411 construction, that is, without hollow parts, as shown in the Confucian diagram in Figure 3. , there were problems as described below.
第1図、第2図に示した半導体スタックの構成に於いて
は、スタッド形半導体素子1の電流のアンバランス、順
電圧降下の違いにより各々の素子の発熱量に相轟のアン
バランスが発生する。このため、冷却フィン2の容量は
順電圧降下の最悪のもの、電流バランスの最悪のケース
を考えた大きさとする必要がある。In the configuration of the semiconductor stack shown in FIGS. 1 and 2, an unbalance in the current of the stud-type semiconductor element 1 and a difference in forward voltage drop cause an unbalance in the amount of heat generated by each element. do. Therefore, the capacity of the cooling fins 2 needs to be sized to take into account the worst case of forward voltage drop and the worst case of current balance.
ところが、従来の如く、冷却フィン2′f:連結するボ
ルト4として第3図に示す様な中実構造のものを用いる
と、半導体スタック上の各位置でvX6図に示す如きm
K分布を示す事となる。これは、ボルト4の熱伝導性の
悪さに起因するものであるが、温度分布をならそうとす
ると冷却フィン2の大きさは必然的に大きくなり、重量
増を伴うものとなってしまう。また、各々の冷却フィン
2でも素子近傍と遠い部分では温度差が大きくなりフィ
ン効率を低下させることとなってしまうため、必要な性
能を確保するためには、更にフィン形状を大型化する必
要があった。このため、半導体スタック自体の大型化と
重量増は避けられず、何らかの対策が必要とされて来た
。However, if a solid structure as shown in FIG. 3 is used as the cooling fin 2'f: connecting bolt 4 as in the past, m as shown in FIG.
This shows the K distribution. This is due to the poor thermal conductivity of the bolts 4, but if an attempt is made to even out the temperature distribution, the size of the cooling fins 2 will inevitably increase, resulting in an increase in weight. In addition, in each cooling fin 2, the temperature difference between the vicinity of the element and the far part becomes large, reducing the fin efficiency, so in order to secure the necessary performance, it is necessary to further enlarge the fin shape. there were. For this reason, an increase in the size and weight of the semiconductor stack itself is unavoidable, and some countermeasures have been required.
従って、本発明の目的は上記従来技術の欠点を解消し、
スタッド形半導体素子を複数個並列に使用するに当って
、各々の半導体素子毎に設けられた冷却フィンの温度の
均一化と1個の冷却フィンの素子近傍と遠い部分の温度
差の低減を容易に実現し得る半導体スタックを提供する
ことにある。Therefore, the object of the present invention is to overcome the drawbacks of the above-mentioned prior art,
When using multiple stud-type semiconductor devices in parallel, it is easy to equalize the temperature of the cooling fins provided for each semiconductor device and reduce the temperature difference between the near and far parts of the cooling fin. The objective is to provide a semiconductor stack that can be realized in the future.
上記目的を達成するために、本発明に於いては半導体ス
タックを、冷却部材に半導体素子を取付けた素子ユニッ
トを複数個並設して成るユニット群と、冷媒を封入した
中空部を有し、各冷却部材を貫通してこれらを互いに締
付ける締付部材とから構成したものである。In order to achieve the above object, the present invention provides a semiconductor stack having a unit group including a plurality of element units in which semiconductor elements are attached to a cooling member and a hollow part filled with a coolant, It is constructed from a tightening member that penetrates each cooling member and tightens them together.
以下、本発明の1!施例を図面を参照しながら説明する
。Below, 1 of the present invention! Examples will be described with reference to the drawings.
第4図は本発明の一実施例に係る半導体スタッタに運用
される中空ボルト5の部分断面側面図であり、I!5−
は中空ボルト5の縦断面図である。FIG. 4 is a partial cross-sectional side view of a hollow bolt 5 used in a semiconductor stutter according to an embodiment of the present invention. 5-
is a vertical cross-sectional view of the hollow bolt 5.
11!4図、第5図に示した中空ボルト5は基本的には
第1園、纂2図に示す様な構造の半導体スタックに適用
されるものであるが、ソリッドボルト4との違いは、ボ
ルト軸に沿って設けられた中空部5′を真空にした後で
水ヤフロン等の冷媒を封入した構造になっている点にあ
る。11! The hollow bolt 5 shown in Figures 4 and 5 is basically applied to a semiconductor stack having the structure shown in Figures 1 and 2, but the difference from the solid bolt 4 is that The structure is such that a hollow portion 5' provided along the bolt axis is evacuated and then a refrigerant such as water flon is sealed therein.
なお、第8図は纂1図、第2因の構成に対して第4図、
第5図に示す如き中空ボルト5を適用した上で纂2図A
−A@でとった断面図であるが、この場合、冷却フィン
2と中空ボルト5との熱伝導性をよくするために1両者
のすきまに熱伝導性パテ6を充てんしである。In addition, Fig. 8 is a summary of Fig. 1, and Fig. 4 is for the configuration of the second cause.
After applying the hollow bolt 5 as shown in Fig. 5,
This is a cross-sectional view taken at -A@, and in this case, in order to improve the thermal conductivity between the cooling fins 2 and the hollow bolts 5, the gap between the cooling fins 2 and the hollow bolts 5 is filled with thermally conductive putty 6.
かかる構成に於いて、中空ボルト5は各冷却フィン2間
に温度差がある場合にはヒートパイプとして働き、温度
差を少な(する方向に熱を輸送する。また、1個の冷却
フィン2の中に於いても、温度差がある場合には中空ボ
ルト5により温度差を少なくする方向に熱が輸送される
。In this configuration, when there is a temperature difference between each cooling fin 2, the hollow bolt 5 acts as a heat pipe and transports heat in a direction that reduces the temperature difference. Even inside, if there is a temperature difference, the hollow bolt 5 transports heat in a direction that reduces the temperature difference.
その結果、半導体スタック上の各位置で@7図に示す如
<、1!6図の温度分布と比較して位置による温度差の
少ない温度分布を得ることが出来るものである。このよ
うに、冷却フィン2を貫通した中空ボルト5により、各
々の冷却フィン2の温度差は、中空ボルト5の内部で蒸
発、蒸気移動、凝縮を繰り返す冷媒の作用によりほとん
どなくなる。As a result, it is possible to obtain a temperature distribution at each position on the semiconductor stack, as shown in Figure 7, with less temperature difference depending on the position compared to the temperature distribution shown in Figures 1 and 6. In this way, with the hollow bolts 5 penetrating the cooling fins 2, the temperature difference between the respective cooling fins 2 is almost eliminated by the action of the refrigerant that repeats evaporation, vapor movement, and condensation inside the hollow bolts 5.
これにより、冷却フィン2の大きさは半導体素子1)I
IE!5!アンバランス等を考厘するウェイトが少なく
なるため、形状は小さくなり、また軽量化の上でも効果
的である。また、1個の冷却フィン2の中でも温度分布
が改善されるのでフィン効率が上がり、冷却フィン2の
小型化が可能となる。As a result, the size of the cooling fins 2 is determined by the size of the semiconductor element 1) I
IE! 5! Since there is less weight to account for imbalance, the shape is smaller and it is also effective in reducing weight. Furthermore, since the temperature distribution within one cooling fin 2 is improved, the fin efficiency is increased and the cooling fin 2 can be made smaller.
なお、中空ボルト5の取付方間によっては内部にウィッ
クを入れてもよい。また、中空ボルト5の代りに第9図
の部分断面側面図に示す如き両ねじスタッド7を用いれ
ばスタックそのものの小形、軽量化を行うに当ってこれ
を容易に実現することが出来る。Note that a wick may be inserted inside depending on how the hollow bolt 5 is attached. Furthermore, if a double threaded stud 7 as shown in the partial cross-sectional side view of FIG. 9 is used instead of the hollow bolt 5, the stack itself can be made smaller and lighter.
また、ヒートパイプ用の中空部を有する中空ボルト5な
いしは両ねじスタッド7を製作するに轟っては、ヒート
パイプt−埋め込む構造としても、中空部5′の埋め栓
5Aに予め細管を接続し、これを通して真空引きや冷媒
注入を実施し、最後に細管を封じ切った構造としてもよ
い◎
〔発明の効果〕
以上述べた如く、本発明によれば、スタンド形半導体素
子を取付けられた冷却フィンf:複数個連結するボルト
ないしはスタッドを中空とし、中に冷媒を封入すること
によって、gjA度分布の均一化を実現し、その結果と
して小製、芸量化の実施上可能ならしめた半導体スタッ
クを得ることが出来る。In addition, when the hollow bolt 5 or the double-threaded stud 7 having a hollow part for a heat pipe is manufactured, a thin tube can be connected in advance to the plug 5A of the hollow part 5' to form a structure in which the heat pipe is embedded. , through which evacuation or refrigerant injection may be carried out, and finally the thin tube may be sealed.◎ [Effects of the Invention] As described above, according to the present invention, a cooling fin to which a stand-type semiconductor element is attached is provided. f: By making the bolts or studs that connect multiple bolts or studs hollow and filling them with refrigerant, we have achieved a uniform gjA degree distribution, and as a result, we have created a semiconductor stack that can be made smaller and more sophisticated. You can get it.
第1図、第2図は周知の半導体スタックの構造を示す正
面図及び平面図、
第3図は従来の半導体スタックに用いられて来たボルト
40儒1iX−1
114図は本発明の一実施例に係る半導体スタックに適
用される中空ボルトの部分断面側面図、第5図は1!4
図の中空ボルトの縦断面図、@6図は従来の半導体スタ
ックに於ける温度分布の説明図。
#!7図は本発明の実施例に係る半導体スタックの温度
分布の説明図、
1!8図は第1図、第2図の構成に中空ボルトを適用し
た場合に、第2図のA−A線で得た断面図、第9図は中
空構造を有する両ねじスタッドの部分断面側面図である
。
1−・スタッド形半導体素子、2・−冷却フィン、4・
・・ソリッドボルト、5・−中空ボルト。
出願人代理人 猪 股 清1 and 2 are a front view and a plan view showing the structure of a well-known semiconductor stack. FIG. 3 is a bolt 40F1iX-1 used in a conventional semiconductor stack. A partial cross-sectional side view of a hollow bolt applied to a semiconductor stack according to an example, FIG. 5 is 1!4
The vertical cross-sectional view of the hollow bolt shown in the figure, @6 is an explanatory diagram of the temperature distribution in a conventional semiconductor stack. #! Fig. 7 is an explanatory diagram of the temperature distribution of the semiconductor stack according to the embodiment of the present invention, and Figs. FIG. 9 is a partially sectional side view of a double threaded stud having a hollow structure. 1--Stud type semiconductor element, 2--Cooling fin, 4-
・・Solid bolt, 5.-Hollow bolt. Applicant's agent Kiyoshi Inomata
Claims (1)
並設して成るユニフシ群と、冷#&t−封入した中空部
を有し、各冷却部材を貫通してこれらを互いに締付ける
締付部材とから成ることを4$11にとする半導体スタ
ック。 2、締付部材が冷却部材に穿設された穴を貫通して設け
られる中空ボルトから成ることt−特徴とする特許請求
の範H第1項に記載の半導体スタック。 3、冷却部材の穴が熱伝導性パテを介して中空ボルトと
轟接している9とヲ4I黴とする特許請求の範囲第2項
に記載の半導体スタック。[Scope of Claims] 1. A unit group consisting of a plurality of element units each having a semiconductor attached to a cooling member arranged side by side, and a hollow portion filled with cold #&T, and penetrating through each cooling member to connect these. A semiconductor stack consisting of a clamping member that clamps each other together costs $4.11. 2. The semiconductor stack according to claim H, wherein the fastening member comprises a hollow bolt provided through a hole drilled in the cooling member. 3. The semiconductor stack according to claim 2, wherein the hole in the cooling member is in contact with the hollow bolt through a thermally conductive putty.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2856282A JPS58147049A (en) | 1982-02-24 | 1982-02-24 | Semiconductor stack |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2856282A JPS58147049A (en) | 1982-02-24 | 1982-02-24 | Semiconductor stack |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58147049A true JPS58147049A (en) | 1983-09-01 |
Family
ID=12252074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2856282A Pending JPS58147049A (en) | 1982-02-24 | 1982-02-24 | Semiconductor stack |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58147049A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5300810A (en) * | 1990-10-03 | 1994-04-05 | Norton Company | Electronic circuit and method with thermal management |
-
1982
- 1982-02-24 JP JP2856282A patent/JPS58147049A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5300810A (en) * | 1990-10-03 | 1994-04-05 | Norton Company | Electronic circuit and method with thermal management |
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