JPS58146193A - Communication system between processors - Google Patents

Abstract

PURPOSE:To reduce the load to a call control processor (CPR) so as to process effective control information only for the CPU, by providing a flag representing the effectiveness with the control information from a lot of line control processors (LPRs). CONSTITUTION:The line control information including a flag bit representing the effectiveness transmitted from a lot of the LPRs (not shown) in the order of the LPR number is sequentially stored in a signal memory RSM1 according to the address representing the LPR number from a count circuit CNT1. The said flag bit 1 is given to a count circuit CNT2 in the control information, and a number memory RSM2 addressed with the output of the circuit CNT2 stores the device number of the LPRs trasmitting effective control information from the CNT1. The CPR (not shown) reads out the effective control information only from the RSM1 based on the LPR number of the RSM2.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a processor customization system, in particular a plurality of line control processors each controlling a plurality of times 111iI, and a signal memory from a plurality of line control processors. The present invention relates to a method for communicating between Norosef in a distributed control multiplex four-processor switch and a call control processor that executes call processing based on control information transmitted through the switch.

佽）Prior art and problems FIG. 1 is a diagram showing an example of a distributed AM multipresence switch which is the object of the present invention. In FIG. 1, a plurality of line units (LS) and , each time −
A network NW connected to the unit LS by a highway HwK, and a call control processor CPR that controls the network NW and connects it to each other by exchanging times are shown. A line control function tLPR is provided to monitor and control the status of a plurality of MLs via each line. Communication information (e.g. audio) for each session IIL is Section III, Section 16Lc.
The signal is PCM-encoded at , placed in the communication time slot of the highway HW via the φ-responsible m circuit MPX, and transmitted to the network NW. Note that the line control information necessary for switching connection transmitted from each line control processor tLPR to the call control processor CPR is also placed in the time slot of highway aWOg and transmitted to the network NW. In network NW, each time - two days) L
Hike from S.

i HW is converted into multiple highway MH by multiple conversion circuit MPX.
Converted to W. The communication information of each line carried by the speech time slot of the multi-highway MHW is sequentially stored in the speech path memo 9SPM, and the line control information carried by the signal time slot is stored in the received signal. Memo uR8MK oJI stored sequentially
ToL yy is a diagram showing an example of the line control information.
F is set to the value 1 when line control information is valid for exchange 1III#. The received signal memory R8
The previous line control information stored in M is sent to the signal reception distribution device t8R.
All information is transmitted to the call control processor by Do control. Call control program? The CPR extracts and analyzes line control information effective for traffic control from the line control information transmitted from the signal reception and distribution device SRD, and sends the communication path memory SPMOa*output address to the control memory CM in the network NW. The line control information to be transmitted to the 1g1i1 control processor LPR is stored in the trusted signal memory SSM via the signal reception and distribution device SRD to execute the required switching connection.

As is clear from the above explanation, the conventional processor LP
All the line control information of P is transmitted to the call control processor CPR, and its validity is judged by the call control processor CPR one by one. This results in a decrease in performance.

(a) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional inter-processor communication system as described above, and reduce the load required for the call control processor to receive the control information from the line control processor. The purpose of this invention is to realize an inter-processor communication system that can reduce the number of lines as much as possible and improve processing performance. In a distributed control multiprocessor exchange equipped with a call control processor that executes call processing based on line control information received from the line control processor via a signal message, the line transmitted from the line control processor is Means is provided for classifying a flag bit indicating the validity of the line control information included in the control information Kt and storing the number of the line control processor that transmitted the valid line control information, and the call control processor This is accomplished by referring to the number given and extracting only valid V-line control information from the signal memory.

(・) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an inter-processor communication system according to an embodiment of the present invention, and FIG. 84 is a diagram showing an example of the signal sequence in FIG. 3. The same objects are indicated by the same reference numerals throughout the figures. In addition, in FIG. 3, the total number of line control processors tLPR ([Im) is 256, and the format of the line control information carried from each line control processor tLPR to the signal time slots of the highway MW and multiple highway MHW is as follows. As shown in Figure 2, the size is 8 bits x 4 bytes. In Figure 3, each time m t14
Control processor LPRO to LPR255 (0 to 255
The line control information transmitted from each line control processor I, PR) is transmitted from the multiple highway M
Received signal memory R from HW (Figure 1) via small number DAT
It arrives at the signal memory R5Ml in AM, and each time it arrives -
The signals are sequentially stored in addresses inputted from the incrementing counting circuit CNT1 via the signal 11b and the selector 5ELIt. Note that the address (10
The upper 8 bits of the 8 bits are stored and are the numbers 0 to 255 of the line control processor LPH that sent out the previous line control information.
corresponds to

The line control information Pb7 is also transmitted to G via the signal 11A&'. As shown in FIG. 4, the cough gate G is in a conductive state according to the logic value IK inputted from the signal line C in synchronization with the line control information BO),
pi) BO's flag pi) F in b7 is signal 4
It is input to the counting circuit CNT2 via Id. The cough counting circuit CNT2 advances by a small step when the yiji filling value 1 (7 lag bits) F is input, that is, when the valid line control information 1/& arrives, and passes through the signal line and the selector 5KLZ. input the address into number memory R8M2. A counting circuit CNT is connected to the skeleton code memory R8M2 via a signal line b'.
1 to line control processor LPR number 0 to 255
is transmitted, the number transmitted when the address is input from the counting layer CNT2, that is, the valid line control information is sent out, and only the number of the nine line allocation processor LPH is sequentially stored in the number memo IJBBM2. Ru. At the time when the line control information @ (old group I) transmitted from all line control processors LPRO to LPR25B is stored in the signal memory R8MI, the number memory lJR8M2 has the above 256
Among the set of line control information, the number of the line control processor LPH that is the sender of valid line information is stored. Once the 256 sets of line control information have been stored in 1BM1, the call control processor CPR sends the leading address to the number memory R8M2Kfi as the output address via the signal reception distribution device sRD, the signal Mf and the selector 5EL2. Input the number of the line control processor LPH stored in the cough start address and send the signal 11! kg and is extracted via the signal reception and distribution device SRD. The call control processor CPR sequentially inputs the address obtained by adding the lower two bits (t-) to the extracted number (8 bits) of the line control processor LPH to the signal memory R8MI via the signal reception distribution device SRD, the signal line and the selector 5ELI. death,
Valid line control information (4 pies) is sequentially extracted via the signal reception distribution device via the signal line it. In this way, after extracting the - set of valid line control information, the call control processor CPR advances the read address input in the number memory R8M2 by one step and reads the address of the line control processor LPR stored next to the earlier application address. Extract the number, Homare-11
1, a set of historically effective line control information is extracted from the signal memory R8MI in the same process as described above. Similarly, the call control process ytcPRti signal memory RAM1
Sequentially extracts the valid line control information stored in the number memo ') 18M2 and sends out the valid line control information stored in 18M2. When all the numbers of the fi1 allocation processor LPH have been extracted nine times, , ending the extraction of line control information from the signal memory lJR8M1 0 As is clear from the above description, according to this embodiment, the call control processor CPR extracts the number of the line control processor LPH that sent the valid line control information. By referring to the number memory storing the line, only valid time m1tltI control information is extracted from the signal memory R8MI.
The load of the present invention must be reduced to a minimum.
! For example, the target line control processor fl
, the number of PRs and the format of the 1 ml control information are not limited to those illustrated, and many other modifications may be considered, but the effects of the present invention will not change in any case. Furthermore, the configuration of the distributed control i-multiprocessor exchange to which the present invention is applied is not limited to that shown in the drawings.

(f) Effects of the Invention According to the present invention, in the distributed control multiprocessor exchange, the load required for the call control processor to receive the line control t# information from the line control processor is reduced to a minimum, and the processing capacity is increased. can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a distributed control multiprocessor switch that is a target of the present invention, FIG. I@2 is a diagram showing an example of (b)m control information, and FIG. FIG. 4 is a diagram showing an example of the signal 7 in FIG. 3. In the figure, L is a line and LS is a line unit. LC is a line circuit, and LPR is a line control processor. MPX and DMPX are multiple conversion circuits, MW is highway, NW is network, MHW is multi-highway, S
PM Hiro communication route memo'j, RAM is injury signal memo! j, S
SM is a transmission signal memo LCM is a control memo! J and SRD are signal reception and distribution devices, CPR is a call control processor, F is a flag bit, and D is data. BO to B3 are pi), bo to b7 are bits. R8MI is signal memory* 18M2 is number memory, C
NT1 and CNT2 are needle count circuits, 5IL1 and 8E
L2 represents a selector, and a to i represent signal lines. Spear 1 Figure yJ2- Figure

Claims (1)

[Claims] The system includes a plurality of line control processors each controlling a plurality of @ lines, and a call control processor executing a call control based on line control information transmitted from the plurality of line control processors via a signal memory. In the distributed control multiprocessor switch, the bladder bit indicating the validity of the line control information included in the line control information transmitted from the circuit control process ν is identified, and the bladder bit indicating the validity of the line control information transmitted from the circuit control process ν is identified, and the bladder bit indicating the validity of the line control information transmitted from the circuit control A processor clearance value system, characterized in that means is provided for storing numbers of control processors, and the call control processor refers to the stored numbers and extracts only valid line control information from the signal memory.