JPH0759097B2 - Communication method between processors in electronic exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] In the present invention, a state change occurs in each of a plurality of lower processors distributed in an electronic exchange, and in each of a plurality of hardware subordinate to the lower processor. Each time the status change is collected and stored as hardware-compatible, the processor in the electronic exchange enables the host processor to efficiently monitor and identify the hardware related to the status change and the status change. It relates to an intercommunication method.

[Background of the Invention]

In the past, in electronic exchanges with a relatively large line scale, in order to avoid concentration of processing load on a specific processor, for example, dedicated processors monitor and control subscriber terminals, and functions are distributed by multiple processors. This is the case as it is. Specifically, in order for each lower processor to control each of a plurality of pieces of hardware under it, it is necessary for each lower processor to transfer state change information for each piece of hardware to the upper processor. The upper processor also controls the hardware as desired through each of the lower processors based on the state change information. However, in the case where the functions are distributed by the multiprocessor, on the other hand, on the other hand, a new problem occurs. When the host processor confirms the presence or absence of the state change information individually for each piece of hardware by the monitoring program, and when each existing state change information is monitored and identified, a dynamic step in the monitoring program is performed. It cannot be denied that the processing capacity of the upper processor will decrease as the number of lower processors or the hardware under the lower processors increases as a result. Has become. Incidentally, the technique described in Japanese Patent Laid-Open No. 59-214352 has some problems as described above.

[Object of the Invention]

An object of the present invention is that, each time a state change occurs in each of a plurality of subordinate processors arranged in the electronic exchange, a change in the state is regarded as hardware compatible. It is an object of the present invention to provide an interprocessor communication method in an electronic exchange in which a host processor can efficiently monitor and identify hardware related to a state change in a state of being collected and stored.

[Outline of Invention]

The above-mentioned object is that in each lower processor, each time there is a state change in any of a plurality of hardware subordinate to the lower processor, the state change is stored as corresponding to the hardware and the status register is also stored. In the master status register under the control of the lower processor, the lower processor corresponding identification flag in the master status register is set to the "1" state. On the other hand, while being set, the upper processor, which periodically monitors the state of the lower processor corresponding identification flag in the master status register, sends a message from the lower processor for which the identification flag is in the "1" state every time it identifies the lower processor. Read the contents of the status register and identify from the contents of the status register Each time the hardware lug is in the "1" state is identified from the processor is accomplished by a state change that is stored as of the hardware corresponding loads.

Example of Invention

 The present invention will be described below with reference to FIGS. 1 to 5.

First, an electronic exchange according to the present invention will be described.
The figure shows the configuration of an example of the electronic exchange. As shown in the figure, in the present example, each of a large number of subscriber terminals T including telephone terminals is accommodated in a corresponding terminal control processor (terminal controller) TC,
The status change of each accommodated subscriber terminal T detected by each TC is used as monitoring data, and the interface circuit INT and the highway H are used by the communication method having a simple protocol.
W _{0 to} HW ₇ , switches SW _{0 to} SW _m , communication control unit (communication controller, corresponding to lower processor) CC ₀ to CC _m , transferred to main processor (corresponding to upper processor) CP via system controller SC On top of that
It is monitored and identified by the main processor CP.
By the way, according to the present invention, at this time, the state change from the corresponding terminal control processor TC, which is once received and stored in each of the communication control devices CC _{0 to} CC _m , is followed by the main processor.
It has a characteristic content depending on whether it is monitored and identified after being transferred to the CP.

More specifically, on the highways HW ₀ to HW ₇ ,
While the monitoring data from each terminal control processor TC toward the main processor CP is transferred via the monitoring channel CHi using the specific channel (i-th time slot) CHi on the upstream highway as the monitoring channel,
The control data from the main processor CP to each terminal control processor TC has a specific channel (i-th time slot) CHi on the downlink highway as a control channel.
It has been transferred via the control channel CHi.
That is, the switch SW ₀ to SW _m each, on monitoring data is extracted from the monitoring channel CHi on upward highway, while being transferred to the communication control device CC ₀ to CC _m each, the communication control unit CC ₀ ~ Control data from each CC _m switch SW ₀
Each of SW _m is inserted into the control channel CH i on the downlink highway. Incidentally, the format of the supervisory channel CHi will be described later with reference to FIG.

FIG. 2 shows a communication control device CC _j , C as a main part according to the present invention.
C _k (j, k = 0 to m), system controller SC
The register configuration of each is shown. As shown, highways HW _{0 to} HW ₇ are provided in the communication control devices CC _j and CC _k .
Receive buffer HW where monitoring data from each is temporarily stored
RB _{0 to} HWRB ₇ , control data registers HWREG _{0 to} HWREG ₇ in which control data from the main processor CP is temporarily stored, and highways HW _{0 to} HW ₇ corresponding to the presence or absence of monitoring data reception from the highway. The status register SREG shown (8 bits) is provided. Further, in the system controller SC, the communication control device CC ₀
Corresponding to each CC _m , a master status register MSREG (m + 1 bit) indicating whether or not the monitoring data is received by the communication control device is provided. More specifically, in the status register SREG, bits corresponding to each of the highways HW _{0 to} HW ₇ are provided.
When the monitoring data is actually received from the highway HW _k (k = 0 to 7), only the bit k corresponding to the highway is set to the “1” state.
The presence / absence of reception of the monitoring data from each of HW _{0 to} HW ₇ can be referred to by the main processor CP. Also,
Communication control device CC ₀ in the master status register MSREG
~ CC _m is provided with a bit corresponding to each, when the monitoring data is received by any of the communication control device CC ₀ ~ CC _m , by the communication control device, the bit corresponding to the communication control device Is set to the “1” state, the presence / absence of reception of the monitoring data in each of the communication control devices CC _{0 to} CC _m can be referred to by the main processor CP. After all, when the main processor CP periodically monitors and identifies the monitoring data, first, among the m + 1 bits in the master status register MSREG, to confirm whether or not the monitoring data is received by each of the communication control devices CC _{0 to} CC _m. , Which bit is in the “1” state is confirmed. If any of the bits are in the "0" state, no monitoring data is stored in the communication control devices CC _{0 to} CC _m , so the monitoring identification process is terminated as it is and the monitoring identification in the next cycle is performed. To prepare for. If there is more than one bit in the "1" state, the bit state in the status register SREG in the communication control device corresponding to that bit is referenced for the first time, and there is at least one "1" state. From each bit, the highway for receiving the monitoring data is known, and the monitoring data is read from the corresponding receiving buffer into the main processor CP, whereby the monitoring data is first identified for monitoring.

Explaining the format of the supervisory channel CHi, the supervisory channel CHi is positioned as the i-th time slot on the ascending highway, as can be seen from the overall time division multiplexing frame format shown in FIG. The time slots other than the i-th time slot are set for transfer of voice and the like, and the monitor data from the terminal control processor TC is transferred in the switch direction via the monitor channel CHi. Such a situation is the same when control data is transferred from the switch to the terminal control processor TC on the down highway. By the way, the format in the monitoring channel CHi is shown in detail in FIG. 3, and in this case, the format is an 8-bit header (synchronization bit indicating the frame head), an 8-bit data length (data size (byte Number)), 8-bit control code (frame type / name), 8-bit address (device address of main processor CP as communication partner), and data (data to main processor CP as communication partner (variable length) )) Is composed of.

FIG. 4 shows a method of receiving and storing the monitor data in the communication control device CC _j when the monitor data is actually received from the highway HW _k (k = 0 to 7). . Although overlapping with the above explanation, when the monitoring data is received from the highway HW _k , the status register SREG
Above, only the bit k corresponding to that highway HW _k is “1”.
At the same time is set to a state, which is assumed to received monitored data are temporarily stored in the receive buffer HWRB _k of the highway HW _k corresponding. Also in this case, on the master status register MSREG by the communication control device CC _j, the communication control device CC _j corresponding bit is assumed to be set to "1" state.

Now, FIG. 5 shows a flow of the monitoring target data monitoring program according to the present invention, and the processing by the program will be described as follows.

That is, in the main processor CP, the program itself is started at a constant cycle (for example, 4 ms cycle), but when it is started, the contents of the master status register MSREG are first read from the system controller SC. Whether or not all the bits in the master status register MSREG are in the "0" state is determined (for example, by the hardware detection by the exclusive OR gate and the detection result). . When all the bits are in the “0” state, the monitoring data is not received and stored in any of the communication control devices CC _{0 to} CC _m , so that the monitoring identification process of the monitoring data is immediately ended. However, when one or more bits are in the "1" state, the communication control device corresponding to these bits sequentially outputs the status register MSREG.
The contents are read out and then processed in a predetermined manner. That is, every time the content of the status register SREG is read, the highway related to the monitoring data reception is known from each of the bits in the “1” state, which exists in the status register SREG one or more, and the monitoring data from the corresponding reception buffer. Is read into the main processor CP, and the monitoring data is first monitored and identified.

Finally, considering the effect of the present invention on the above-mentioned embodiment, if it is said that (m +
1) For 8 highways, the communication control devices CC _{0 to} C ₀ to determine whether or not there is monitoring data corresponding to the highways.
Each time the main processor CP directly reads the contents of the status register SREG from each C _m, the presence or absence of the monitoring data is sequentially judged from the state of each bit corresponding to the highway on the status register SREG, and the monitoring data is If it exists, the monitoring data is read from the corresponding receiving buffer to the main processor for the first time, and the processing such as the monitoring identification processing is repeated.
Many processing steps and time were required for the Chinese poem identification processing. However, according to the invention,
For example, assuming that the monitoring program is started at a cycle of 4 ms, the probability that the monitoring data will be received becomes smaller as the monitoring cycle becomes smaller in each time span in which the time period is set to 4 ms. , When the contents of the master status register MSREG are referenced in a 4 ms period, it is extremely rare that all the (m + 1) bits on the master status register MSREG are in the "1" state, and rather, those (m + 1) bits. Are all in the "0" state, or at best, only a very small number of those (m + 1) bits are sporadically placed in the "1" state. Therefore, first, referring to the contents of the master status register MSREG, the contents of the status register SREG are sequentially read out from the communication control device corresponding to that bit only for a very small number of bits in the "1" state. Therefore, the increase of the dynamic step is suppressed, and the subscriber terminal T related to the state change and the state change can be efficiently monitored and identified by the main processor CP.

〔The invention's effect〕

As described above, in the case of the present invention, each time a state change occurs in each of a plurality of subordinate processors arranged in the electronic exchange, a change in the state occurs in each of a plurality of hardware subordinate thereto. Is collected and stored as hardware compatible, the upper processor can efficiently monitor and identify the hardware related to the state change and the state change.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an example of an electronic exchange according to the present invention, FIG. 2 is a diagram showing a register configuration in each of its main parts, and FIG. 3 is a diagram showing the present invention in FIG. FIG. 4 is a diagram for explaining monitoring target data in such an example, FIG. 4 is a diagram for explaining a method of receiving and storing the monitoring target data in a main part, and FIG. 5 is a monitoring target data according to the present invention. It is a figure which shows the flow of the program for monitoring. T …… Terminal, TC …… Terminal monitoring control processor, INT ……
Interface circuit, CHi ... Monitoring channel, HW _{0 to} HW ₇
...... Highway, SW _{0 to} SW _m ...... Switch, CC _{0 to} CC _m ......
The communication control apparatus (subordinate processor), SC ...... system controller, CP ...... main processor (host processor), SREG ...... status register, MSREG ...... master status register, HWRB ₀ ~HWRB ₇ ...... receive buffer.

Claims (1)

[Claims] 1. A plurality of lower processors distributed in an electronic exchange, each time a state change occurs in each of a plurality of hardware subordinate to the lower processor, the state change corresponds to the hardware. A method for interprocessor communication in an electronic exchange for efficiently monitoring and identifying hardware related to a state change and the state change by a host processor in a state of being collected and stored as an entity, in each of the lower processor , Every time there is a state change in any of the plurality of hardware subordinate to the lower processor, the state change is stored as corresponding to the hardware, and the hardware corresponding identification flag in the status register is A master that is set to the "1" state and that is under the control of the lower processor and is under the control of the upper processor The lower processor corresponding identification flag in the status register is set to the "1" state, while the upper processor periodically monitoring the state of the lower processor corresponding identification flag in the master status register has the identification flag set to "1". Each time a lower processor in the 1 "state is identified, the contents of the status register are read from the processor, and every time the hardware whose identification flag is in the" 1 "state is identified from the contents of the status register, the processor reads from the processor. Is a method for interprocessor communication in an electronic exchange, wherein a state change stored as being compatible with the hardware is read.