JPS58146138A - Noise suppression system - Google Patents

Noise suppression system

Info

Publication number
JPS58146138A
JPS58146138A JP2935282A JP2935282A JPS58146138A JP S58146138 A JPS58146138 A JP S58146138A JP 2935282 A JP2935282 A JP 2935282A JP 2935282 A JP2935282 A JP 2935282A JP S58146138 A JPS58146138 A JP S58146138A
Authority
JP
Japan
Prior art keywords
latch
level
output
triggered
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2935282A
Other languages
Japanese (ja)
Inventor
Masamitsu Tanaka
真実 田中
Hiroyuki Takekura
武倉 弘幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd, Nippon Victor KK filed Critical Victor Company of Japan Ltd
Priority to JP2935282A priority Critical patent/JPS58146138A/en
Publication of JPS58146138A publication Critical patent/JPS58146138A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/34Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
    • H03G3/345Muting during a short period of time when noise pulses are detected, i.e. blanking

Abstract

PURPOSE:To suppress noises having steep level change, by operating a squelch circuit, when a level change of an input signal deteced at a fixed period is larger than a fixed threshold value predetermined. CONSTITUTION:After an RF signal at a terminal 1 is rectified at a rectifier 2, the signal is converted at an A/D converter and latched to a latch 4. Data v0 is stored in the latch 4. When a clock (a) from a clock generator 5 rises at a time T0.5, a monostable multivibrator 6 and a latch 7 are triggered, and the data v0 stored in the latch 4 is loaded to the latch 7. At a time T1.0, the output (b) of the monostable multivibrator 6 falls down, a monostable multivibrator 3, the latch 4 and the A/D converter 3 are triggered and the data v1 of the latch 4 and the output v0 of the latch 7 are supplied to an attenuator 8. The difference DELTAv1-0 is compared with a threshold value VTH at a comparator 9 and when DELTAv1-0>VTH, then a retriggerable multivibrator 11 is triggered, goes to an H level for DELTAtsec and the squelch circuit is turned on.

Description

【発明の詳細な説明】 本発明は雑音抑圧方式に係り、一定時間内の入力信号レ
ベルの変化量を一定の閾値と比較し、ノイズと正規の信
号とを明確に区別してノイズのみを確実に抑圧し得る雑
音抑圧方式を提供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise suppression method, which compares the amount of change in input signal level within a certain period of time with a certain threshold value, clearly distinguishes between noise and normal signals, and reliably suppresses only noise. The purpose is to provide a noise suppression method that can suppress noise.

一般に、従来のFM受信機は無信号時のノイズや低レベ
ルのノイズが出力されることを防止するためにRFレベ
ルそのものを一定の閾値と比較し、RFレベルが閾値よ
り小になった時スケルチ回路を駆動してノイズを抑圧し
ていた。
In general, conventional FM receivers compare the RF level itself with a certain threshold in order to prevent noise when there is no signal or low-level noise from being output, and squelch when the RF level becomes lower than the threshold. The noise was suppressed by driving the circuit.

ところで、近年、FM受信機の近傍でマイクロコンピュ
ータ等発生するノイズの周波数帯域が広く、かつ、その
レベルが高い機器が使用されることが多い。このような
レベルの高いノイズが発生される機器の近くでFM受−
信機を用いると、上記の如きRFレベルそのものを閾値
と比較する従来の方法では、例えばこの閾値レベル以上
の高レベルのノイズが入来した場合等、スケルチ回路が
作動せず、このノイズを完全に抑圧することは困難であ
る欠点があった。
Incidentally, in recent years, devices such as microcomputers that generate noise in a wide frequency band and at a high level are often used in the vicinity of FM receivers. Do not install an FM receiver near equipment that generates such high-level noise.
With the conventional method of comparing the RF level itself with a threshold value, for example, when high-level noise exceeding the threshold level comes in, the squelch circuit does not operate and the noise cannot be completely eliminated. had drawbacks that were difficult to suppress.

本発明は上記欠点を除去したものであり、以下図面と共
にその一実施例について説明する。
The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to the drawings.

第1図は本発明になる雑音抑圧方式の一実施例のブロッ
ク系統図を示す。同図において、端子lに入来した第2
図に示す如きRF倍信号整流器2にて整流されてDCレ
ベルとされた後、A/D変換器3にてデジタル信号に変
検され、ラッチ4にラッチされる。今、ラッチ4にデー
タV。(第3図@)がストアさねているとする。第3図
囚に示す9口く、時刻T。5でクロック発生器5からの
クロツりaが立上ると、単安定マルチバイブレータ(以
下、モノマルチという)6及びラッチ7は同図(ト)。
FIG. 1 shows a block diagram of an embodiment of the noise suppression method according to the present invention. In the same figure, the second
The signal is rectified into a DC level by an RF double signal rectifier 2 as shown in the figure, converted into a digital signal by an A/D converter 3, and latched by a latch 4. Now, data V is in latch 4. Suppose that (Fig. 3 @) is trying to store. At the 9th time shown in Figure 3, time T. When the clock signal a from the clock generator 5 rises at step 5, the monostable multivibrator (hereinafter referred to as monomulti) 6 and latch 7 are activated as shown in FIG.

(qに示す如く順にトリガされ(モノマルチ6及びラッ
チ7は共に入力信号の立上りでトリガされる)、これに
より、ラッチ4にストアされているデータVOは同図(
Qに示す如くラッチ7にロードされる。
(The data VO stored in the latch 4 is triggered in the order shown in q (both the monomulti 6 and the latch 7 are triggered by the rising edge of the input signal), and the data VO stored in the latch 4 is triggered as shown in the figure (
It is loaded into latch 7 as shown in Q.

ラッチ4の出力データV。及びラッチ7の出力データv
oは共に減算器8に供給されて比較され、その差Δv 
o−oが取り出される。差Δv0−〇は、第3図(ト)
に示す如く、 ΔVO−0=  l VO(ラッチ4)−vO(ラッチ
7)に 〇 であり、コンパレータ9に供給される。コンパレータ9
にて基準電圧発生器10からの一定の閾値電圧VTR(
デジタル値)と減算器8からの出力Δv o−oとが比
較され、この場合vTH〉ΔvO−0故、コンパレータ
9からはLレベル信号が取り出される。・これにより、
再トリガモノマルチ11はトリガされず、この時点が以
前にトリガがかかつてその出力がHレベルになった時点
からワンショット時間Δを枕内であればその出力はHレ
ベルのままで、出力端子12に接続さねているスケルチ
回路(図示せず)のオン状態を保持する一方、この時点
が以前にトリガがかかつてその出力がHレベルになった
時点からワンショット時間Δを秒経過後(その出力はL
レベルになり、スケルチ回路はオフになる)であればそ
の出力はLレベルのままで、スケルチ回路のオフ状態を
保持する。いずれの場合も、スケルチ回路の状態を反転
させることはない。
Latch 4 output data V. and output data v of latch 7
o are both supplied to the subtractor 8 and compared, and the difference Δv
oo is taken out. The difference Δv0−〇 is shown in Figure 3 (G)
As shown in , ΔVO-0=l VO (latch 4) - vO (latch 7) is 0, and is supplied to the comparator 9. Comparator 9
A constant threshold voltage VTR (
(digital value) and the output Δv o-o from the subtractor 8 are compared, and in this case, since vTH>ΔvO-0, an L level signal is taken out from the comparator 9.・Thus,
The re-trigger monomulti 11 is not triggered, and if this point is within the one-shot time Δ from the time when the trigger was previously activated and its output went to H level, its output remains at H level and the output terminal While maintaining the on state of the squelch circuit (not shown) connected to 12, one-shot time Δ seconds has elapsed from the time when the trigger was previously fired and its output became H level ( Its output is L
level and the squelch circuit is turned off), the output remains at the L level and the squelch circuit is kept in the off state. In either case, the state of the squelch circuit is not reversed.

時刻T 1.0になるとモノマルチ6の出力すが立下り
、この立下りでモノマルチ13、ラッチ4及びA/Di
換器3は力負にトリガされ(モノマルチ13は入力信号
の立下りでトリガされ(第3図(ト))、ラッチ4及び
A/D変換器3は入力信号の立上りでトリガされる)、
第3図(匂に示すクロ<、A/D変換器3の出力データ
v1がラッチ4にロードされてここにストアされる。こ
のときのラッチ4の出力v1とラッチ7の出力voとが
減算器8に供給され、差Δv1−(、は、第3図T)に
示すy口く、ΔVl−o  =  I  Vx(9yチ
4)  −Vo(yyテy)  1となる。この差ΔV
l−0はコンパレータ9に供給されて闇値VTRと比較
され、ΔVl−0> VTHであればコンパレータ9の
出力はHレベルとされ、再トリガモノマルチ11はトリ
ガされる。これにより、梧トリガモノマルチ11の出力
はワンショット時間Δを秒だけI(レベルとなり、スケ
ルチ回路はオン状態となる。
At time T 1.0, the output of the mono multi 6 falls, and at this fall, the mono multi 13, latch 4 and A/Di
The converter 3 is triggered on the negative side (the monomulti 13 is triggered on the falling edge of the input signal (Fig. 3 (g)), and the latch 4 and A/D converter 3 are triggered on the rising edge of the input signal). ,
The output data v1 of the A/D converter 3 is loaded into the latch 4 and stored there. At this time, the output v1 of the latch 4 and the output vo of the latch 7 are subtracted. 8, and the difference Δv1-(, is shown in Figure 3T) becomes ΔVl-o = I Vx (9y 4) - Vo (yy ty) 1. This difference ΔV
l-0 is supplied to the comparator 9 and compared with the dark value VTR, and if ΔVl-0>VTH, the output of the comparator 9 is set to H level, and the re-trigger monomulti 11 is triggered. As a result, the output of the Go trigger monomulti 11 becomes I (level) for one shot time Δ seconds, and the squelch circuit is turned on.

一方、ΔVl−0< VTHであればコンパレータ9の
出力はLレベルとされ、再トリガモノマルチ11はトリ
ガされない。この時点が以前にトリガがかかつてその出
力がHレベルになった時点からワンショット時間Δを枕
内であればその出力はHレベルのままで、スケルチ回路
のオン状態を保持する一方、この時点が以前にトリガが
かかつてその出力がHレベルになった時点からワンショ
ット時間Δを秒経過後であればその出力はLレベルのま
まで、スケルチ回路のオフ状態を保持する。
On the other hand, if ΔVl-0<VTH, the output of the comparator 9 is set to L level, and the retrigger monomulti 11 is not triggered. If this point is within the one-shot time Δ from the point when the trigger was previously fired and the output went to H level, the output will remain at H level and the squelch circuit will remain on, while at this point If the one-shot time Δ seconds has elapsed since the trigger was previously fired and the output became H level, the output remains at L level, and the squelch circuit remains in the OFF state.

次に時刻T1.5でクロックaが立上るとモノマルチ6
、ラッチ7はトリガされ、これにより、ラッチ4にスト
アさ社ているデータv1はラッチ7にロードされる。ラ
ッチ4のデータv1とラッチ7のデータv1とが減金(
器8に供給され、その差Δv1−1が取り出される。こ
の差Δv1−1は、第3図(稍に示す如く、 ΔVt−x  ””  I  vtDyチ<l  −v
l(yyチyl  l二 〇 である。この場合、VTH〉Δv1−1であるため、上
記時刻To5の場合と同様に丹トリガモノマルチ11は
トリガされず、スケルチ回1洛は1駆動されない。
Next, when clock a rises at time T1.5, the monomulti 6
, latch 7 is triggered, causing data v1 stored in latch 4 to be loaded into latch 7. Data v1 of latch 4 and data v1 of latch 7 are reduced (
8, and the difference Δv1-1 is taken out. This difference Δv1-1 is expressed as ΔVt-x ''I vtDy<l-v
In this case, since VTH>Δv1-1, the red trigger mono multi 11 is not triggered and the squelch is not driven once, as in the case of time To5.

以後、時刻T2.0 + T2.5 + T3.0 +
  も上記の場合と同様の動作が繰返され、ラッチ4の
出力とラッチ7の出力との差Δvn−(n−1) ” 
”n −vn−1が1値vTHよりも大の時にスケルチ
回路か駆動される。
From then on, time T2.0 + T2.5 + T3.0 +
The same operation as in the above case is repeated, and the difference between the output of latch 4 and the output of latch 7 is Δvn-(n-1).
``When n-vn-1 is greater than one value vTH, the squelch circuit is driven.

つまり、本j唄発明は、ノイズのレベル変化は一般に正
規の信号のレベル変化に比して急激である点に着目しで
ある一定時間内の)LFレベル変化童を一定の閾11哩
と比較している。このため、正規の信号の場合はレベル
変化量は1ml値と比較すると小さいので、これにより
、スケルチ回路を動作させることはなく、一方、高レベ
ルのものも含むノイズの場合はレベル変化量は閾値と比
較すると大きいので、これによりスケルチ回路を駆動し
得、特に高レベルのノイズを正規の信号と明確に区別し
゛て高レベルのノイズを確実に抑圧するようにしている
In other words, this invention focuses on the fact that noise level changes are generally more rapid than regular signal level changes, and compares the LF level change (within a certain period of time) with a certain threshold of 11 m. are doing. Therefore, in the case of a regular signal, the amount of level change is small compared to the 1ml value, so the squelch circuit will not be activated.On the other hand, in the case of noise, including high-level ones, the amount of level change will be the threshold value. Since the signal is large compared to the normal signal, this can drive a squelch circuit to clearly distinguish high-level noise from a normal signal, thereby reliably suppressing high-level noise.

なお、時刻’ro、s 〜T1.0の期間、時刻Tt、
s 〜Tz。
Note that the period from time 'ro,s to T1.0, time Tt,
s~Tz.

の期間、・は減算器8の出力Δvn−11はクロックに
同期して必ず0とされ、コンパレータ9の出力もそれと
同期してLレベルとされる。このため、VTH〈Δvn
−in−11 = vn−vn−□が成立するよう・な
高いレベルの信号が入来した時でもコンパレータ9の出
力はクロックaに同期してHレベルとLレベルとを繰返
され、又、RFレベルの値が時間に対して極値をもつこ
とを考えれば極値で減算器8の出力はOとなるのでコン
パレータ9の出力は極値毎をこI(レベルとLレベルと
を繰返される。そこで、このコンパレータ9の出力のH
レベルとLレベルとの毎にスケルチ回路をスイッチング
していたのでは切換ノイズが音声出力に与える影響を無
視し得なくなるため、再トリガモノマルチ11に一定時
間のワンショット時間Δを秒(時刻T11 ””’ T
n+1の期間の例えば500倍程度)を設定しておき、
−雇スケルチ回路がオンすればこの状態を保持できるよ
うに構成されている。
During the period, the output Δvn-11 of the subtracter 8 is always set to 0 in synchronization with the clock, and the output of the comparator 9 is also set to the L level in synchronization with it. For this reason, VTH〈Δvn
Even when a high-level signal such as -in-11 = vn-vn-□ is input, the output of the comparator 9 repeats H level and L level in synchronization with clock a, and RF Considering that the level value has an extreme value with respect to time, the output of the subtracter 8 becomes O at the extreme value, so the output of the comparator 9 changes for each extreme value (level and L level are repeated). Therefore, the output of this comparator 9 is
If the squelch circuit is switched for each level and L level, the effect of switching noise on the audio output cannot be ignored. ””' T
For example, about 500 times the period of n+1),
- It is constructed so that this state can be maintained if the squelch circuit is turned on.

上述の如く、本発明になる雑音抑圧方式は、入力信号の
レベルを一定周期毎に検出して一定時間内のレベル変化
量を得、このレベル変化量を予め定められた一定の閾値
と比較してこの変化量が閾値よりも犬の時スケルチ回路
を動作させるため、一般にレベル変化が比較的急激であ
るノイズと一般にレベル変化が比収的緩かである正規の
信号とを明確に区別し得、例えば、FM受信機等に適用
した場合、コンピュータ等からのレベルの高いノイズと
これと同程度のレベルの正規の信号とを区別してノイズ
発生の場合だけスケルチ回路を確実に動作させ得、RF
レベルそのものをある周期毎に一定の閾値と比較してス
ケルチ回路を動作させていた従来方式に比して基レベル
のノイズを雉突に抑圧し得る等の特長を有する。
As described above, the noise suppression method according to the present invention detects the level of an input signal at regular intervals to obtain the amount of level change within a certain period of time, and compares this amount of level change with a certain predetermined threshold. Since the squelch circuit operates when the amount of change in the lever is greater than the threshold, it is possible to clearly distinguish between noise, which generally has relatively rapid level changes, and regular signals, which generally have relatively slow level changes. For example, when applied to an FM receiver, etc., it is possible to distinguish between high-level noise from a computer, etc. and a regular signal of the same level, and to operate the squelch circuit reliably only in the case of noise generation.
Compared to the conventional method in which a squelch circuit is operated by comparing the level itself with a fixed threshold value every certain period, this method has the advantage of being able to dramatically suppress base level noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方式の一実施例のブロック系統図、第2
図はRFレベルの変化状態を示す図、第3図囚〜nは本
発明方式の動作説明用タイミングチャートである。 1・・Φ入力端子、2@・・整流器、3・・・A/D変
換器、4,7@II・ラッチ、5・拳・クロック発生i
、6,13・・・単安定マルチバイブレータ、8・0減
算器、9・・・コンパレータ、10・・・基準電圧発生
器、11・・・再トリガ単安定マルチバイブレータ、1
2・・・出力端子。
FIG. 1 is a block diagram of an embodiment of the method of the present invention, and FIG.
The figure shows a state of change in the RF level, and FIGS. 3-3 are timing charts for explaining the operation of the system of the present invention. 1... Φ input terminal, 2 @... Rectifier, 3... A/D converter, 4, 7 @ II, latch, 5, fist, clock generator i
, 6, 13... Monostable multivibrator, 8.0 subtractor, 9... Comparator, 10... Reference voltage generator, 11... Retrigger monostable multivibrator, 1
2...Output terminal.

Claims (1)

【特許請求の範囲】[Claims] 入力信号のレベルを一定周期毎に検出して一定時間内の
レベル変化量を得、該レベル変化量を予め定められた一
定の閾値と比較して該レベル変化量が該閾値よりも大の
時スケルチ回路を動作させることを性徴とする雑音抑圧
方式。
Detect the level of the input signal at regular intervals to obtain the amount of level change within a certain period of time, compare the amount of level change with a certain predetermined threshold, and when the amount of level change is greater than the threshold A noise suppression method whose characteristic is operating a squelch circuit.
JP2935282A 1982-02-25 1982-02-25 Noise suppression system Pending JPS58146138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2935282A JPS58146138A (en) 1982-02-25 1982-02-25 Noise suppression system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2935282A JPS58146138A (en) 1982-02-25 1982-02-25 Noise suppression system

Publications (1)

Publication Number Publication Date
JPS58146138A true JPS58146138A (en) 1983-08-31

Family

ID=12273813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2935282A Pending JPS58146138A (en) 1982-02-25 1982-02-25 Noise suppression system

Country Status (1)

Country Link
JP (1) JPS58146138A (en)

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