JPS58146139A - Noise suppression system - Google Patents

Noise suppression system

Info

Publication number
JPS58146139A
JPS58146139A JP2935382A JP2935382A JPS58146139A JP S58146139 A JPS58146139 A JP S58146139A JP 2935382 A JP2935382 A JP 2935382A JP 2935382 A JP2935382 A JP 2935382A JP S58146139 A JPS58146139 A JP S58146139A
Authority
JP
Japan
Prior art keywords
level
data
latch
signal
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2935382A
Other languages
Japanese (ja)
Inventor
Masamitsu Tanaka
真実 田中
Hiroyuki Takekura
武倉 弘幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd, Nippon Victor KK filed Critical Victor Company of Japan Ltd
Priority to JP2935382A priority Critical patent/JPS58146139A/en
Publication of JPS58146139A publication Critical patent/JPS58146139A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference

Abstract

PURPOSE:To suppress noised having a high level giving an adverse effect on a normal signal, by operating a squelch circuit when a level change of an input signal is larger than a threshold value in response to an average circuit of the input signal level. CONSTITUTION:An RF signal at a terminal 1 is rectified at a rectifier 2, converted at an A/D converter 3 and latched to a latch 4. Data vn is stored in a latch 4 at a time Tn. A memory 5 is a shift register storing (m+1) sets of data, and (m+1) sets of data vn...vn-m before the time Tn are stored, the data vn... vn-m are added at an average circuit 6, and divided with (m+1) and the average data Xn is picked up. Data Xn is supplied to a reference voltage generator 7, where a positive constant is multiplied into alphaXn=vn and supplied to a comparator 8. In this case, an output Vn+1 of the latch 4 and a latch Vn are supplied to a subtractor and the difference DELTAvn+1-1 is compared with the threshold value vn at a comparator 8.

Description

【発明の詳細な説明】 本発明は雑音抑圧方式に係り、一定時間内の入力信号レ
ベルの変化量を一定時間内の入力信号レベルの平均値I
こ応じた閾値と比較し、正規の信号にこの信号に影響を
与える程度のレベルの高いノイズを重畳された信号が入
来した場合に雑音抑圧しり1略を動作させ得る雑音抑圧
方式を提供することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise suppression method, in which the amount of change in the input signal level within a certain period of time is calculated from the average value I of the input signal level within the certain period of time.
To provide a noise suppression method capable of operating a noise suppression function when a signal in which high-level noise that affects a normal signal is superimposed on a normal signal is compared with a corresponding threshold value. The purpose is to

一般に、従来のFM受信機は、無信号時のFMノイズや
低レベルのノイズが出力されることを防止するためにR
Fレベルそのものを一定の閾値と比較し、RFレベルが
閾値より小になった時スケルチ回路を駆動してノイズを
抑圧していた。
Generally, conventional FM receivers use R to prevent FM noise when there is no signal or low-level noise from being output.
The F level itself is compared with a certain threshold, and when the RF level becomes smaller than the threshold, a squelch circuit is driven to suppress noise.

ところで、近年、FM受信機の近傍でマイクロコンピュ
ータ等発生するノイズの周波数帯域が広く、かつ、その
レベルが高い機器が使用されることが多い。このような
レベルの高いノイズが発生される機器の近くでFM受信
機を用いると、上記の如きRFレベルそのものを閾値と
比較する従来の方法では、例えばこの閾値レベル以上の
高レベルのノイズが入来した場合等、スケルチ回路が作
動せず、このノイズを完全に抑圧することは困難である
欠点があった。
Incidentally, in recent years, devices such as microcomputers that generate noise in a wide frequency band and at a high level are often used in the vicinity of FM receivers. If an FM receiver is used near a device that generates such high-level noise, the conventional method of comparing the RF level itself with a threshold value, for example, will detect that high-level noise exceeding this threshold level is being input. The problem is that the squelch circuit does not operate when noise occurs, making it difficult to completely suppress this noise.

そこで、本出願人はこの欠点を除去すべく本願と同日付
で特許出願「雑音抑圧方式」を提案し、た。
Therefore, in order to eliminate this drawback, the present applicant proposed and filed a patent application entitled "Noise Suppression Method" on the same date as the present application.

このものは、入力信号のレベルを一定周期毎に検出して
一定時間内のレベル変化量を得、このレベル変化量を予
め定められた一定の閾値と比較してレベル変化量が閾値
よりも大の時スケルチ回路を動作させる方式であり、ノ
イズと正規の信号とを明確に区別してノイズのみを確実
に抑圧し得るものである。
This device detects the level of the input signal at regular intervals to obtain the amount of level change within a certain period of time, and compares this amount of level change with a certain predetermined threshold to determine if the amount of level change is greater than the threshold. This is a method in which the squelch circuit is operated when the noise is clearly distinguished from the normal signal, and only the noise can be reliably suppressed.

ところで、例えば正規の信号にこの信号に対してレベル
が充分低い(正規の信号に対して悪影響のない)ノイズ
を重畳された信号が入来した場合、このノイズを重畳さ
れた信号のRFレベル変化量はノイズのみのそれと略同
程度である。然るに、上記本出願人が提案した方式では
、レベル変化量を一定の閾値と比較しているだけである
ので、正規信号に対して悪影響のないノイズを重畳され
た信号までもノイズとみなしてスケルチ回路を動作させ
てしまい、必要な信号までも抑圧させてしまう問題点が
あった。
By the way, for example, if a signal is superimposed on a normal signal with noise whose level is sufficiently lower than that of the normal signal (no adverse effect on the normal signal), the RF level of the signal superimposed with this noise will change. The amount is approximately the same as that of noise only. However, in the method proposed by the applicant, the amount of level change is simply compared with a certain threshold, so even signals that are superimposed with noise that does not have an adverse effect on the normal signal are considered to be noise and are not squelched. This has the problem of causing the circuit to operate and even suppressing necessary signals.

本発明は上記問題点を解決したものであり、以下図面と
共にその一実施例について説明する。
The present invention solves the above problems, and one embodiment thereof will be described below with reference to the drawings.

第1図は本発明になる雑音抑圧方式の一実施例のブロッ
ク系統図を示す。同図において、端子1に入来した第2
図に示す如きRF倍信号整流器2にて整流されてDoレ
ベルとされた後、A/D変換器3にてデジタル信号に変
換され、ラッチ4にラッチされる。今、時刻Tnでラッ
チ4にデータV (第3図(E))がストアされている
とする。メモリ5は(m+1)個のデータをストアでき
るシフトレジスタ形のもので、第2図に示す如く、時刻
Tnでは時刻Tnから(m+ 1 )個のデータをスト
アしている期間遡った時刻Tl+、迄のデータ(つまり
(m+1)個のデータ) Vn% Vn−□がストアさ
れており、この(milli固のデータV。−vn−□
は平均化回路6に供給されて加算され、かつ、(m+1
)で割算されて平均データXnが取り出される。データ
X。は基準電圧発生器7に供給さねて正の定数αを乗じ
られてαXo−vn(デジタル値)とされ、このV。(
第3図(0)は閾1直としてコンパレータ8に供給され
る。
FIG. 1 shows a block diagram of an embodiment of the noise suppression method according to the present invention. In the same figure, the second
After being rectified by the RF double signal rectifier 2 as shown in the figure and set to Do level, it is converted to a digital signal by the A/D converter 3 and latched by the latch 4. It is now assumed that data V (FIG. 3(E)) is stored in the latch 4 at time Tn. The memory 5 is of a shift register type that can store (m+1) pieces of data, and as shown in FIG. The data up to (that is, (m+1) pieces of data) Vn% Vn-□ is stored, and this (milli-specific data V.-vn-□
are supplied to the averaging circuit 6 and added, and (m+1
) to extract the average data Xn. Data X. is supplied to the reference voltage generator 7 and multiplied by a positive constant α to obtain αXo−vn (digital value), and this V. (
3(0) is supplied to the comparator 8 as the threshold value 1.

第3区内に示す如く、時刻T二でクロック発生器9から
のクロックaが立上ると、単安定マルチバイブレータ(
以下、モノマルチという)10及びラッチ11は同図Q
3) 、 (0)に示す如く順にトリガされ(モノマル
チ10及びラッチ11は共に入力信号の立上りでトリガ
される)、これにより、ラッチ4にストアされているデ
ータvnは同図(0に示す如くラッチ11にロードされ
る。ラッチ4の出力データvn及びラッチ11の出力デ
ータvnは共に減算器12に供給されて比較され、その
差Δvn−0が取り出される。差ΔvIm−nは、第3
図(CIに示す如く、 ハn−n  ”  l  vn(ラッチ4)−vn(ラ
ッチ11)1= 0 であり、コンパレータ8に供給される。コンパレータ8
にて基準電圧発生器7からの閾値電圧VQと減算器12
からの出力Δvn−0とが比較され、この場合はVn〉
Δvn−7故、Lレベル信号が取り出される。
As shown in the third section, when the clock a from the clock generator 9 rises at time T2, the monostable multivibrator (
(hereinafter referred to as mono-multi) 10 and latch 11 are Q in the same figure.
3) The data vn stored in the latch 4 is triggered in the order shown in (0) (both the monomulti 10 and the latch 11 are triggered at the rising edge of the input signal), and as a result, the data vn stored in the latch 4 is triggered as shown in the figure (0). The output data vn of the latch 4 and the output data vn of the latch 11 are both supplied to the subtracter 12 and compared, and the difference Δvn-0 is extracted.The difference ΔvIm-n is
As shown in FIG.
The threshold voltage VQ from the reference voltage generator 7 and the subtractor 12
is compared with the output Δvn−0 from Vn>
Since Δvn-7, an L level signal is taken out.

これにより、再トリガモノマルチ13はトリガさねず、
この時点が以前にトリガがかかつてその出力がHレベル
になった時点からワンショット時間Δを枕内であればそ
の出力はHレベルのままで、出力端子14に接続されて
いるスケルチ回路(図示せず)のオン状態を保持する一
方、この時点が以前にトリガがかかってその出方がHレ
ベルにな 、つた時点からワンショット時間Δを秒経過
後(その出力はLレベルになり、スケルチ回路はオフに
なる)であればその出力はLレベルのままで、スケルチ
回路のオフ状態を保持する。いずれの場合も、スケルチ
回路の状態を反転させることはない。
As a result, the retrigger monomulti 13 will not be triggered,
If this point is within the one-shot time Δ from the time when the trigger was previously fired and its output went to H level, the output remains at H level, and the squelch circuit connected to the output terminal 14 (Fig. (not shown) remains on, while at this point the output goes to H level due to previous triggering, and after one-shot time Δ seconds have elapsed (its output goes to L level and the squelch output goes to H level). (the circuit is turned off), its output remains at the L level, maintaining the off state of the squelch circuit. In either case, the state of the squelch circuit is not reversed.

時刻Tn+1になるとモノマルチ10の出力bが立下り
、この立下りでモノマルチ15、ラッチ4、A/D変換
器3、メモリ5及び平均化回路6は順にトリガされ(モ
ノマルチ15は入力信号の立下りでトリガされ(第3図
(至))、ラッチ4 、A/D変換器3.メモリ5及び
平均化回路6は入力信号の立上りでトリガされる)、第
3図(6)に示す如< % A/D変換器3の出力デー
タvn+1がラッチ4及びメモリ5にロードされてここ
に夫々ストアされる。これにより、メモリ5は時刻Tn
−□にストアされたデータvn−□がなくなり、時刻T
。+l−mから時刻TIl++1ま、での(m+1)個
のデータvn+1−□〜vn+1がストアされたことに
なる。上記の場合と同様に、このデータvn+1−m 
” vn+1は平均化回路6にて加算され、かつ、割算
されて平均データXfl+1とされ、基準電圧発生器7
にて第3図(ト)に示す如き閾値vn+1とされてコン
パレータ8に供給される。
At time Tn+1, the output b of the monomulti 10 falls, and at this fall, the monomulti 15, latch 4, A/D converter 3, memory 5, and averaging circuit 6 are triggered in order (the monomulti 15 receives the input signal The latch 4, A/D converter 3, memory 5 and averaging circuit 6 are triggered at the rising edge of the input signal (Fig. 3 (to)), and the latch 4, A/D converter 3, memory 5, and averaging circuit 6 are triggered at the rising edge of the input signal. As shown, the output data vn+1 of the A/D converter 3 is loaded into the latch 4 and memory 5 and stored therein. As a result, the memory 5 stores the time Tn
The data vn-□ stored in −□ disappears, and time T
. This means that (m+1) pieces of data vn+1-□ to vn+1 from +l-m to time TIl++1 are stored. Similar to the above case, this data vn+1−m
” vn+1 is added in the averaging circuit 6 and divided to obtain average data Xfl+1, which is then sent to the reference voltage generator 7.
The threshold value vn+1 is then supplied to the comparator 8 as shown in FIG.

このときのラッチ4の出力vn+1とラッチ11の出力
V。とが減算器12に供給され、差Δvn+1−11は
、第3図(qに示す如く、 Δvn+1−n ” l vn+1+?ff4)  −
vn(PF?+1) 1となる。この差Δvn+t−n
はコンパレータ8に供給されて閾値■n+1と比較され
、Δv、1−n > Vn+1であればコンパレータ8
の出力はHレベルとされ、再トリガモノマルチ13はト
リガされる。これにより、再トリガモノマルチ13の出
力はワンショット時間Δを秒だけHレベルとなり、スケ
ルチ回路はオン状態となる。
At this time, the output vn+1 of latch 4 and the output V of latch 11. is supplied to the subtractor 12, and the difference Δvn+1-11 is calculated as follows, as shown in FIG.
vn(PF?+1) becomes 1. This difference Δvn+t−n
is supplied to the comparator 8 and compared with the threshold ■n+1, and if Δv,1-n > Vn+1, the comparator 8
The output of is set to H level, and the retrigger monomulti 13 is triggered. As a result, the output of the retrigger monomulti 13 becomes H level for one shot time Δ seconds, and the squelch circuit is turned on.

一方、Δvn+1−n<Vo+1であればコンパレータ
8の出力はLレベルとされ、再トリガモノマルチ13は
トリガされない。この時点が以前にトリガがかかつてそ
の出力がHレベルにならた時点からワンショット時間Δ
を枕内であればその出力はHレベルのままで、スケルチ
回路のオン状態を保持する一方、この時点が以前にトリ
ガがかかつてその出力がHレベルになった時点からワン
ショット時間Δを秒経過後であればその出力はLレベル
のままで、スケルチ回路のオフ状態を保持する。
On the other hand, if Δvn+1-n<Vo+1, the output of the comparator 8 is set to L level, and the retrigger monomulti 13 is not triggered. This point is the one-shot time Δ from the point when the trigger was previously fired and its output became H level.
If it is within the pillow, the output will remain at H level and the squelch circuit will remain on, while the one-shot time Δ will be set in seconds from the time when the trigger was previously triggered and the output went to H level. After the elapse of time, the output remains at the L level and the squelch circuit remains in the off state.

次に、時刻T、、+1でクロックaが立上るとモノマル
チ10、ラッチ11はトリガされ、これにより、ラッチ
4にストアされているデータV。+1はラッチ11にロ
ードされる。ラッチ4のデータvn+1とラッチ11の
データvn+1とが減算器12に供給され、その差ハ(
n++ 1−(n+x lが取り出される。この燈ΔY
(n+tl−(n+11は第3図(qに示す如く、 Δv(n+1)−in+tl”  l vnet(ラッ
プ4)     n+ll?クテエ1)に〇 である。vn+1〉Δv(n+11−(。+1)である
ため、上記時刻耳の場合と同様に再トリガモノマルチ1
3はトリガされず、スケルチ回路は駆動されない。
Next, when the clock a rises at time T,,+1, the monomulti 10 and the latch 11 are triggered, and the data V stored in the latch 4 is thereby triggered. +1 is loaded into latch 11. Data vn+1 of latch 4 and data vn+1 of latch 11 are supplied to subtracter 12, and the difference between them is (
n++ 1-(n+x l is taken out. This light ΔY
(n+tl-(n+11 is 0 in Figure 3 (as shown in q, Δv(n+1)-in+tl"l vnet(lap 4) n+ll?cute 1).vn+1>Δv(n+11-(.+1) Therefore, as in the case of the time ear above, re-trigger mono multi 1
3 is not triggered and the squelch circuit is not driven.

以後、時刻Tn+2 + Tn+21 Tn+31 ”
’も上記の場1′1゜ 合と同様の動作が繰返され、あるレベル観測時点におけ
るラッチ4のデータ出力とラッチ11のデータ出力との
差がその観測時点より(m+1)個前のデータ分遡った
時点迄の平均レベルに応じた閾値よりも大の時にスケル
チ回路が駆動される。
From then on, time Tn+2 + Tn+21 Tn+31”
The same operation as in the above case 1'1 is repeated, and the difference between the data output of latch 4 and the data output of latch 11 at a certain level observation point is equal to (m+1) data points before that observation point. The squelch circuit is activated when the level is higher than the threshold value corresponding to the average level up to the point in time.

つまり、本願発明は、正規の信号にこの信号に影響を与
えない程度のレベルのノイズを重畳された信号(信号人
という)の平均値レベルに応じた閾値とこの信号中のあ
る点からある点迄のレベル変化量との差と、正規の信号
にこの信号に悪影響を与える程度のレベルの高いノイズ
を重畳されたイコ号(或いは高レベルのノイズのみ)(
信号Bという)の平均値レベルに応じた閾値とこの信号
中のある点からある点迄のレベル変化量との差とには大
きな隔りがあることに着目し、あるレベル観測点におけ
るRFレベルとその一つ前のレベル観測点におけるRF
レベルとのレベル変化量をその観測点より一定時間遡っ
た時点迄のレベルの平均値に応じた閾値と比較している
。このため、上記信号Aの場合、この信号Aのレベル変
化量はこの4g@Aの閾値よりも小さくこれにより、ス
ケルチ回路を駆動させることはなく、一方、上記信号B
の場合、この信号Bのレベル変化量はこの信号Bの閾値
よりも大きくこれにより、スケルチ回路を駆動し得、こ
れら両信号を明確に区別して信号Bの場合のみ受信機か
らのノイズを抑圧するようにしている。
In other words, the present invention provides a threshold value corresponding to the average level of a signal (referred to as a signal person) in which noise of a level that does not affect the normal signal is superimposed, and a point from a certain point in this signal to a certain point. The difference between the amount of level change up to this point and the equal signal (or only high level noise) with high level noise superimposed on the normal signal to the extent that it has a negative effect on this signal (
Focusing on the fact that there is a large difference between the threshold value corresponding to the average level of signal B) and the amount of level change from a certain point in this signal to a certain point, we can calculate the RF level at a certain level observation point. and RF at the previous level observation point
The amount of change in level is compared with a threshold value that corresponds to the average value of the level up to a certain time back from the observation point. Therefore, in the case of the signal A, the amount of change in the level of the signal A is smaller than the threshold value of 4g@A, so that the squelch circuit is not driven, and on the other hand, the signal B
In this case, the amount of change in level of this signal B is greater than the threshold value of this signal B, which can drive the squelch circuit, clearly distinguishing between these two signals, and suppressing noise from the receiver only in the case of signal B. That's what I do.

なお、時刻T二〜Tn+、の期間、時刻TI+1〜Tn
+2の期間、・・・は減算器12の出力はクロックに同
期して必ず0とされ、コンパレータ8の出力もそれと同
期してLレベルとされる。このため、v〈ΔV(減算器
12の出力)が成立するような高いレベルの信号が入来
した時でもコンパレータ8の出力はクロックaに同期し
てHレベルとLレベルとを繰返され、又、RFレベルが
時間に対して極値をもつことを考えれば極値で減算器1
2の出力はOとなるのでコンパレータ8の出力はHレベ
ルとLレベルとを繰返される。そこで、このコンパレー
タ8の出力のHレベルとLレベルとの毎にスケルチ回路
をスイッチングしていたのでは切換ノイズが音声出力に
与える影響を無視し得なくなるため、再トリガモノマル
チ13に一定時間のワンショット時間Δを秒(例えば時
刻Tn ” Tfillの期間の例えば500倍程度)
を設定しておき、一度スケルチ回路がオンすればこの状
態を保持できるように構成されている。
Note that the period from time T2 to Tn+, and the period from time TI+1 to Tn
During the +2 period, the output of the subtracter 12 is always set to 0 in synchronization with the clock, and the output of the comparator 8 is also set to L level in synchronization with it. Therefore, even when a high level signal such as v<ΔV (output of the subtracter 12) is input, the output of the comparator 8 repeats H level and L level in synchronization with clock a, and , considering that the RF level has an extreme value with respect to time, the subtracter 1 at the extreme value
Since the output of the comparator 2 becomes O, the output of the comparator 8 repeats the H level and the L level. Therefore, if the squelch circuit is switched every time the output of the comparator 8 goes H level or L level, the effect of switching noise on the audio output cannot be ignored. Set the one-shot time Δ to seconds (for example, about 500 times the period of time Tn" Tfill)
is set, and once the squelch circuit is turned on, this state can be maintained.

又、本実施例では基準電圧発生器7は平均化回路6の出
力Xをα倍して閾値Vを得る構成とされているが、機器
の特性に応じて他の関係式を用いた構成としてもよい。
Further, in this embodiment, the reference voltage generator 7 is configured to obtain the threshold value V by multiplying the output X of the averaging circuit 6 by α, but it may be configured using another relational expression depending on the characteristics of the device Good too.

上述の如く、本発明になる雑音抑圧方式は、入力信号の
レベルを一定周期毎に検出して一定時間内のレベル変化
量を得、かつ、該検出した時点から該一定時間以上の一
定時間遡った時点までの該入力信号のレベルの平均値に
応じた閾値を得、該レベル変化量を該閾値と比較して該
レベル変化量が該閾値よりも大の時スケルチ回路を動作
させるため、この比較により、正規の信号にこの信号に
影響を与えない程度のレベルのノイズを重畳された信号
の場合このレベル変化量はこの場合の閾値よりも小さく
、一方、正規の信号にこの信号に悪影響を与える程度の
レベルの高いノイズを重畳された信号(或いは高レベル
のノイズのみ)の場合はこのレベル変化量はこの場合の
閾値よりも大きいので、正規の信号にこの信号に悪影響
を与える程度のレベルの高いノイズを重畳された信号の
ノイズ或いは高レベルのノイズのみを抑圧し得、単にレ
ベル変化量を一定の閾値と比較してその比較結果に応じ
てスケルチ回路を駆動する本出願人が同日付で提案した
方式のように正規の信号にこの信号に影響を与えない程
度のレベルのノイズを重畳された信号までノイズそのも
のとみなしてしまう虞れはなく、スケルチ回路を誤動作
させてしまうことはない等の將長を有する。
As described above, the noise suppression method according to the present invention detects the level of an input signal at regular intervals to obtain the amount of level change within a certain period of time, and also detects the amount of change in level within a certain period of time from the point of detection. This method obtains a threshold corresponding to the average level of the input signal up to the point in time, compares the amount of change in level with the threshold, and operates the squelch circuit when the amount of change in level is greater than the threshold. By comparison, in the case of a signal in which noise is superimposed on a normal signal at a level that does not affect this signal, this level change amount is smaller than the threshold in this case; In the case of a signal with high-level noise superimposed on it (or only high-level noise), this level change amount is larger than the threshold in this case, so there is no difference in the normal signal with a level that has a negative effect on this signal. On the same date, the present applicant proposed a method that can suppress only the noise of a signal on which high noise is superimposed or high-level noise, and simply compares the amount of level change with a certain threshold value and drives a squelch circuit according to the comparison result. Unlike the method proposed in , there is no risk that the signal superimposed with noise at a level that does not affect the normal signal will be considered as noise itself, and the squelch circuit will not malfunction. It has a masucho such as.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方式の一実施例のブロック系統図、第2
図は1EtFレベルの変化状態を示す図、第3図(5)
〜(qは本発明方式の動作説明用タイミングチャートで
ある。 l・・・入力端子、2・・・繁流器、3Φ・・A/D変
換器、4,11・・・ラッチ、5・・・メモリ、6・・
・平均化回路、7・・・基準電圧発生器、8・・・コン
パレータ、9・−・クロック発生器、10゜15・・・
単安定マルチバイブレータ、12・1111減算器、1
3・・・再トリガ単安定マルチバイブレータ、14・・
拳出力端子。 第1図 第2図 n@−一◆
FIG. 1 is a block diagram of an embodiment of the method of the present invention, and FIG.
The figure shows the state of change in the 1EtF level, Figure 3 (5)
~ (q is a timing chart for explaining the operation of the method of the present invention. l... input terminal, 2... collector, 3Φ... A/D converter, 4, 11... latch, 5... ...Memory, 6...
・Averaging circuit, 7...Reference voltage generator, 8...Comparator, 9...Clock generator, 10°15...
Monostable multivibrator, 12/1111 subtractor, 1
3... Retrigger monostable multivibrator, 14...
Fist output terminal. Figure 1 Figure 2 n@-1◆

Claims (1)

【特許請求の範囲】[Claims] 入力信号のレベルを一定周期毎に検出して一定時間内の
レベル変化量を得、かつ、該検出した時点から該一定時
間以上の一定時間遡った時点までの該入力信号のレベル
の平均値に応じた閾値を得、該レベル変化量を該閾値と
比較して該レベル変化量が該閾値よりも大の時スケルチ
回路を動作させることを崎微とする雑音抑圧方式。
The level of the input signal is detected at regular intervals to obtain the amount of level change within a certain period of time, and the average value of the level of the input signal from the time of detection to the point of time a certain period of time or more is obtained. A noise suppression method whose purpose is to obtain a corresponding threshold value, compare the level change amount with the threshold value, and operate a squelch circuit when the level change amount is larger than the threshold value.
JP2935382A 1982-02-25 1982-02-25 Noise suppression system Pending JPS58146139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2935382A JPS58146139A (en) 1982-02-25 1982-02-25 Noise suppression system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2935382A JPS58146139A (en) 1982-02-25 1982-02-25 Noise suppression system

Publications (1)

Publication Number Publication Date
JPS58146139A true JPS58146139A (en) 1983-08-31

Family

ID=12273839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2935382A Pending JPS58146139A (en) 1982-02-25 1982-02-25 Noise suppression system

Country Status (1)

Country Link
JP (1) JPS58146139A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993014572A1 (en) * 1992-01-15 1993-07-22 Motorola, Inc. Method and apparatus for broken link detect using audio energy level

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993014572A1 (en) * 1992-01-15 1993-07-22 Motorola, Inc. Method and apparatus for broken link detect using audio energy level
US5349701A (en) * 1992-01-15 1994-09-20 Motorola, Inc. Method and apparatus for broken link detect using audio energy level

Similar Documents

Publication Publication Date Title
CN101673136B (en) Power control unit and on/off method
JP2001526008A (en) Electronic system having a chip with integrated power-on reset circuit with glitch sensor
JPH0582094B2 (en)
US6008672A (en) Input signal reading circuit having a small delay and a high fidelity
JPH05282079A (en) Momentary break processing method
WO2023224658A3 (en) Entangled quantum state receiver
US6385743B1 (en) Method of synchronizing an electronic device for monitoring the operation of a microprocessor, and an electronic device for carrying out the method
US6194913B1 (en) Output circuit for digital integrated circuit devices
AU2005337383A1 (en) A method for the use in a battery alarm of a hearing aid, a circuit for monitoring an electric cell, and a hearing aid with such circuit
JPS58146139A (en) Noise suppression system
US7375506B2 (en) Device for comparing an input signal with a set value and correspondinng electronic circuit
US5506533A (en) Apparatus for generating a monostable signal
US5060178A (en) System for analog-digital-analog conversion
CN217640139U (en) Main control circuit&#39;s awakening circuit and electronic equipment
JPS58146138A (en) Noise suppression system
JPH0119789B2 (en)
JP2003304416A (en) Clamp circuit
US20230369970A1 (en) Voltage generator and voltage generating method thereof
JP2004080534A (en) Vertical synchronization detection circuit
JPH0365878A (en) Synchronizer
JP2984850B2 (en) Receiving machine
JPH0955000A (en) Generation circuit of recording and reproducing control signal and automatic control recording circuit
US20010045848A1 (en) Power-up stable signal detection circuit
JPS6242217A (en) Resetting circuit
JP3211619B2 (en) Ghost removal reference signal detection circuit