JPS5814609A - Amplifier - Google Patents

Amplifier

Info

Publication number
JPS5814609A
JPS5814609A JP56113322A JP11332281A JPS5814609A JP S5814609 A JPS5814609 A JP S5814609A JP 56113322 A JP56113322 A JP 56113322A JP 11332281 A JP11332281 A JP 11332281A JP S5814609 A JPS5814609 A JP S5814609A
Authority
JP
Japan
Prior art keywords
amplifier
signal
output
amplifies
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56113322A
Other languages
Japanese (ja)
Other versions
JPS6355805B2 (en
Inventor
Ryuichi Fukuda
隆一 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Columbia Co Ltd
Original Assignee
Nippon Columbia Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Columbia Co Ltd filed Critical Nippon Columbia Co Ltd
Priority to JP56113322A priority Critical patent/JPS5814609A/en
Publication of JPS5814609A publication Critical patent/JPS5814609A/en
Publication of JPS6355805B2 publication Critical patent/JPS6355805B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce the size of an amplifier, by attenuating the input signal applied to an input terminal by an attenuator to then amplify the attenuated input signal by the 4th amplifier and then adding the output of the 4th amplifier to the input signal of the 3rd amplifier. CONSTITUTION:The 1st amplifier 2 amplifies an input signal e1; the 2nd amplifier 4 amplifies the difference signal between the output signals of the amplifier 2 and the signal e1; and the 3rd amplifier 5 amplifies the sum signal of the output signal of the amplifier 4 and the signal e11. The output signals of the amplifiers 1 and 5 are supplied to a load via the 1st and 2nd impedances 6 and 7 respectively. In this case, an attenuator 10 and the 4th amplifier 11 are provided to secure the virtual coincidence between the phase of an output signal e5' of the 3rd amplifier 5 and the output signal of a load terminal 8. As a result, the output power of the amplifier 2 is supplied to a load resistance 9 with high efficiency with no loss caused at the amplifier 5. Thus the amplifiers 2 and 5 can be miniaturized.

Description

【発明の詳細な説明】 本実−は、フィードホワード増@器の効率の向上に関す
る0    ′ 最近嬉1図omitツイードホヮード増幅器が考えられ
ている。図において第1の増幅器20入力端子は、入力
端子1に!1!絖すると共に第2の増幅111440非
反転入力端子に!I絖し、出力端子aJI11のインピ
ーダンス6を介して出力端子8に接続すると共に減衰器
3を介して第2の増幅1140反転入力端子に接続する
。第3の増幅器5の入力端子は第2の増幅器4の出力端
子に接続し、出力端子状第2のインピーダンス7を介し
て出力端子8に接続する。出力端子8は負荷抵抗9を介
して接地する。以上の構成に於いて、非線形な増幅度を
もつ第1の増幅器2の特性によって発生した歪みを、第
2の増幅器4で取り出し、tIX3の増幅器5で増幅し
、第1のインピーダンス6と第2のインピーダンス7で
前記歪み成分を逆相で合成して打消し、出力端子8には
歪みの、4h出力信号が得られる様に動作する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the efficiency of feedforward amplifiers.Recently, tweed amplifiers have been considered. In the figure, the input terminal of the first amplifier 20 is input terminal 1! 1! At the same time as the second amplifier 111440 non-inverting input terminal! It is connected to the output terminal 8 via the impedance 6 of the output terminal aJI11 and to the inverting input terminal of the second amplifier 1140 via the attenuator 3. The input terminal of the third amplifier 5 is connected to the output terminal of the second amplifier 4 and to the output terminal 8 via a second impedance 7 in the form of an output terminal. The output terminal 8 is grounded via a load resistor 9. In the above configuration, the distortion generated due to the characteristics of the first amplifier 2 having a nonlinear amplification degree is extracted by the second amplifier 4, amplified by the amplifier 5 at tIX3, It operates so that the distortion components are combined in opposite phase and canceled by the impedance 7, and a distorted 4h output signal is obtained at the output terminal 8.

しかし、上述に於いて第3の増幅器5は第1の増幅器2
で発生する歪み成分を扱っているのだから、第3の増幅
器5の出力端子に社信号成分は含まれていない。即ち、
入力端子1に印加される入力信号をelとし、第1の増
幅器2の増幅度を腋形成分と非線形成分に分けて、無歪
成分をA1、歪み成分をDとし、減衰器30減衰比を1
/X 、J 2の増幅度をム2.第3の増幅IIsの増
幅度をム3.第1及び第20インピーダンス番及び7の
インピーダンス値をそれぞれzl及びz2とすると、*
SO増幅器6の出力端子の出力レベル・暴は ここで ム1=に=ム意とすると ・S−→ム3・1   ・−−−−−−−−−−−−−
−−−−−−−−(2)そして、jllの増@@20出
力端子の出力レベルes線 el=ム1 sB + D @1  −−−−−−−−
−−−−−−−−−−− (3)従って とすることによって、第10増幅I!2から発生する歪
拳威分(D・1)が除去されて、出力端子8には歪拳の
無い出力1号が得られるが、上述0式(2)gto増幅
ll1O大亀な出力信号が館工のインピーダンス6を舒
て負荷抵抗9と!2のインビーメンスフに分流されるこ
とにな)、負荷抵抗書のインピーダンス値と、1g2の
インビーメンスフのインピーダンス値の割合によって前
記第10増@器の出力信号〇一部が*SO増幅器50出
力端子に流入し、11g3の増幅器5は大1&発熱を伴
うことKな〉、又この出力電力0fllI失によって第
10増幅器20出力電力を負荷抵抗9に効率良く供給す
ることが出来ず、Ml及びgso増幅器共に大皿な%0
となってしti極めて不経済でもある。
However, in the above, the third amplifier 5 is the first amplifier 2.
Since we are dealing with distortion components generated in the third amplifier 5, the output terminal of the third amplifier 5 does not contain any signal components. That is,
The input signal applied to the input terminal 1 is el, the amplification degree of the first amplifier 2 is divided into an axillary component and a nonlinear component, the undistorted component is A1, the distortion component is D, and the attenuation ratio of the attenuator 30 is 1
/X, the amplification degree of J2 is Mu2. The amplification degree of the third amplification IIs is 3. If the impedance values of the 1st and 20th impedance numbers and 7 are zl and z2, respectively, *
The output level of the output terminal of the SO amplifier 6 is as follows: If we assume that MU1 = MU = S - → MU 3 1 ・−−−−−−−−−−−−−
----------(2) And increase of jll @@20 Output level of output terminal es line el=Mu1 sB + D @1 ----------
−−−−−−−−−−− (3) Therefore, by holding, the tenth amplification I! The distorted fist power (D・1) generated from 2 is removed, and output No. 1 without distorted fist is obtained at the output terminal 8. The impedance of the construction is 6 and the load resistance is 9! A portion of the output signal of the tenth amplifier flows into the output terminal of the *SO amplifier 50 according to the ratio of the impedance value of the load resistance and the impedance value of the impedance of 1g2. However, the amplifier 5 of 11g3 generates a large amount of heat, and due to this loss of output power, the output power of the 10th amplifier 20 cannot be efficiently supplied to the load resistor 9, and both the Ml and gso amplifiers %0
However, it is also extremely uneconomical.

この様な電力損失を減少させる九めには、第2のインピ
ーダンス7のインピーダンス値を負荷抵抗9のインピー
ダンス値に比べて充分に大きな値とすれば良いが、反間
前記の式(4)K示す如く、歪みを打消す為の第30増
41i器5の出力振幅を大きく(ム3を大きく)する必
lIEが生じ、骸#E30増幅器5の電源電圧を非常に
大きな電圧にしな妙ればならない欠点を生じる。
The ninth way to reduce such power loss is to make the impedance value of the second impedance 7 a sufficiently large value compared to the impedance value of the load resistor 9. As shown in the figure, it is necessary to increase the output amplitude of the 30th amplifier 41i (increase the amplifier 3) in order to cancel the distortion, and if the power supply voltage of the #E30 amplifier 5 has to be increased to a very high voltage. It causes disadvantages that should not be avoided.

本発明は、上述の様な欠点を改善した効率O嵐いツイー
ドホワード増幅器を提供するtのである。
The present invention provides an efficient tweed forward amplifier that improves the above-mentioned drawbacks.

第2図に本発明の一笑膣例を示す0図に於いて第1図と
異なる点状、入力端子IK印加され九人力信号を減衰器
10で減衰し九後第40増S器11で増幅して、その出
力を第30増−器50入力信号に加算器12により加算
し九ところだけで参るので、前記第1図と同一機能を有
する部分状同一符号を付してその詳細な説明を省略する
も、減衰器1410減衰比をIAとし、s4の増幅器1
1の増幅度をム4とすると、該第4の増幅器11の出力
端子Oレベル・1!#i ・u ”−”ム4・! に 従って、第30増@器5の出力端子のレベルe51は ここで上式!5)の信号成分のレベルを出力端子8の出
力111号レベルe8と尋しくなる様に、減衰器10と
M4K)増@@11トチ となる様に設定すれば、出力端子lと第30増幅器5の
出力端子のレベルは信号夜分により同柑同レベルで駆動
されるから、第3の増幅器5に対して第1の増幅器2の
大きな出力信号線流入しなくなシ、第2のインピーダン
ス7に流れる電流値17は の歪み成分だけの小さな電流値となる。従って、第1の
増幅4112の出力寛刑0七3の増幅器5で損失するこ
となく、効率良く負荷抵抗9に供給さ鴬るQ この様に、本発弓によれば出力電力は効率良く負荷に供
給されるから、第1の増幅器2%出力電力に応じ九必I
H&少隈の小型な増幅器でも良く、第3の増幅器54同
様に小屋な増幅器でも良い〇開本発明の第2図O実膣例
に於いて、第3の増−aSO出力レベルが出力端子8の
信号レベルに等しくなる様に設定出来るならば、減衰器
10を省略してもか會わないこと紘もちろんである。
FIG. 2 shows an example of the present invention. In FIG. 0, there is a dot shape different from that in FIG. Since the output is added to the input signal of the 30th multiplier 50 by the adder 12 in only 9 steps, the same reference numerals are given to the parts having the same functions as in FIG. Although omitted, the attenuation ratio of the attenuator 1410 is IA, and the amplifier 1 of s4
If the amplification degree of 1 is 4, then the output terminal O level of the fourth amplifier 11 is 1! #i・u ”-”mu4・! Accordingly, the level e51 of the output terminal of the 30th multiplier 5 is expressed by the above equation! If the attenuator 10 and M4K) are set so that the level of the signal component of 5) becomes the output 111 level e8 of the output terminal 8, the output terminal 1 and the 30th amplifier Since the level of the output terminal 5 is driven at the same level by the signal part, the large output signal line of the first amplifier 2 does not flow into the third amplifier 5, and the second impedance 7 The current value 17 flowing through is a small current value corresponding to the distortion component of . Therefore, the output power of the first amplifier 4112 is efficiently supplied to the load resistor 9 without loss in the amplifier 5 of the first amplifier 4112. Thus, according to the present invention, the output power is efficiently supplied to the load resistor 9. Since the first amplifier 2% output power is supplied to
It may be a small amplifier of H&S or a small size, or it may be a simple amplifier like the third amplifier 54. Of course, if the signal level can be set to be equal to the signal level of , the attenuator 10 can be omitted.

【図面の簡単な説明】[Brief explanation of the drawing]

M1図は本発明を適要出来る増@罰の一例を示す回路図
、第2図は本発明の一実施例を示す回路図である。 図中2.4及び5はそれぞれ第1、第2及び第30増@
器、6及び7は第1及び:J2のインピーダンス、9は
負荷抵抗である。 特 許 出願人    日本コロムビア株式会社37
FIG. M1 is a circuit diagram showing an example of an increase @ penalty to which the present invention can be applied, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 2.4 and 5 in the figure are the 1st, 2nd and 30th increase @
6 and 7 are impedances of the first and J2, and 9 is a load resistance. Patent applicant Nippon Columbia Co., Ltd.37

Claims (1)

【特許請求の範囲】[Claims] 人力信号を増幅する第1の増幅器と、皺第1の増幅器の
出力信号と前記人力信号と0差信号を増幅する第2の増
幅器と、鋏第2の増幅器の出方イd号と前記入力信号と
のs41号を増幅す″る第3の増幅器から成〉、前記第
1及び第3の増幅器の出方信号をそれぞれ第1及び第2
のインピーダンスを介して負荷に供給するものとし、前
記第3の増幅器の出力信号の位相を前記負荷端0出方備
号とは埋合せることを特徴とする増幅器。
a first amplifier that amplifies the human power signal; a second amplifier that amplifies the output signal of the first amplifier; a second amplifier that amplifies the zero difference signal from the human power signal; and the output ID of the second amplifier and the input a third amplifier for amplifying the output signals of the first and third amplifiers, respectively.
The amplifier is characterized in that the output signal of the third amplifier is supplied to the load via an impedance of 0, and the phase of the output signal of the third amplifier is offset from the output signal of the load terminal.
JP56113322A 1981-07-20 1981-07-20 Amplifier Granted JPS5814609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56113322A JPS5814609A (en) 1981-07-20 1981-07-20 Amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56113322A JPS5814609A (en) 1981-07-20 1981-07-20 Amplifier

Publications (2)

Publication Number Publication Date
JPS5814609A true JPS5814609A (en) 1983-01-27
JPS6355805B2 JPS6355805B2 (en) 1988-11-04

Family

ID=14609288

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56113322A Granted JPS5814609A (en) 1981-07-20 1981-07-20 Amplifier

Country Status (1)

Country Link
JP (1) JPS5814609A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6198385A (en) * 1984-10-19 1986-05-16 三洋電機株式会社 Display controller
JP2007134847A (en) * 2005-11-09 2007-05-31 Nagano Japan Radio Co Amplifier
JP2007134849A (en) * 2005-11-09 2007-05-31 Nagano Japan Radio Co Amplifier

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4218132A1 (en) 2020-09-28 2023-08-02 QuantalRF AG Amplifier including magnetically coupled feedback loop and stacked input and output stages adapted for dc current reuse

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6198385A (en) * 1984-10-19 1986-05-16 三洋電機株式会社 Display controller
JPH043874B2 (en) * 1984-10-19 1992-01-24
JP2007134847A (en) * 2005-11-09 2007-05-31 Nagano Japan Radio Co Amplifier
JP2007134849A (en) * 2005-11-09 2007-05-31 Nagano Japan Radio Co Amplifier

Also Published As

Publication number Publication date
JPS6355805B2 (en) 1988-11-04

Similar Documents

Publication Publication Date Title
US5838195A (en) Reduction of second order harmonic distortion in high power TWT amplifiers
KR920003626A (en) Nonlinearity Compensation Method in Amplifier Circuit
EP0948130A3 (en) Article comprising a power amplifier with feed forward linearizer using a tracking algorithm
EP0803860A3 (en) A noise reduction circuit, a noise reduction apparatus and a noise reduction method
EP0951139A3 (en) Fast adaptive wideband power amplifier feed forward linearizer using a RLS parameter tracking alogrithm
CN1988560A (en) Echo cancel circuit
JPS5814609A (en) Amplifier
JPS626722Y2 (en)
SE9704284L (en) An amplifier and a method in the power amplifier
US4467288A (en) Distortion-free complemented error feedback amplifier and method
EP0658064A3 (en) Acoustic reproducing apparatus
US4446442A (en) Amplifier circuit
US4195267A (en) Low-level preamplifier circuit
JPH0232829B2 (en)
JPS57160207A (en) Voltage-controlled attenuator
JPH05191157A (en) Balanced input type audio amplifying circuit
JP3347431B2 (en) Signal processing method and signal processing device
JPS5814607A (en) Electric power amplifier
JP2609943B2 (en) Amplifier circuit
JPS55140307A (en) Distortion cancelling amplifying circuit
JPS57164603A (en) Amplifier
JPS6117618Y2 (en)
JPS59134907A (en) Nonlinear signal generating circuit
JPS61134106A (en) Negative feedback amplifier
JPS5775012A (en) Feed forward amplifier