JPS5814564A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5814564A JPS5814564A JP56111946A JP11194681A JPS5814564A JP S5814564 A JPS5814564 A JP S5814564A JP 56111946 A JP56111946 A JP 56111946A JP 11194681 A JP11194681 A JP 11194681A JP S5814564 A JPS5814564 A JP S5814564A
- Authority
- JP
- Japan
- Prior art keywords
- regions
- type
- layer
- transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置、特に、異なる特性のトランジスタ
を同一基板内に構成した半導体装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which transistors with different characteristics are formed on the same substrate.
集積回路装置は近年大規模化が進み、それにともない、
回路機能の上から種々の特性を有するトランジスタ管含
むものが要求されるようにな二ている０例えば、接合容
量の小さいトランジスタと接合容量の大きいトランジス
タの組み合せや、コレクタ飽和抵抗の小さいトランジス
タと高耐圧のトランジスタの組み合せ等、これらの組み
合せは相反する条件であり、従来技術で実現する為には
、トランジスタの面積を極端に変えるとか、製造工程を
複雑にする等で対処して来た。しかし表から、上記の方
法は大規模化、コスト門減に適しないものである。In recent years, integrated circuit devices have become larger in scale, and as a result,
In terms of circuit functionality, transistor tubes with various characteristics are now required. These combinations, such as combinations of voltage-resistant transistors, are contradictory conditions, and in order to achieve them using conventional technology, solutions have been achieved by drastically changing the area of the transistors or complicating the manufacturing process. However, from the table, the above method is not suitable for scaling up and reducing costs.
本発明の目的は、同一基板に、異なる特性の半導採素子
が、面積を変えずに簡単な工程Ｔ゛形成れる半導体装置
を提供するにある。An object of the present invention is to provide a semiconductor device in which semiconductor elements having different characteristics can be formed on the same substrate in a simple process T' without changing the area.
即ち、本発明による半導体装置は、表面側にエピタキシ
ャル層を有する半導体基板を備え、該基板内に複数個の
回路素子を含み、かつ該回路素子が互に他と電気的に分
離された島状領域に含まれ、該複数個の島状領域の小麦
くとも一つの島状領域のエピタキシャル層部が他の島状
領域のエピタキシャル層部と同じ導電型で、かつ異なる
膜質で構成されている。That is, the semiconductor device according to the present invention includes a semiconductor substrate having an epitaxial layer on the surface side, and includes a plurality of circuit elements within the substrate, and the circuit elements are each electrically isolated from each other in the form of an island. The epitaxial layer portion of at least one of the plurality of island-like regions included in the plurality of island-like regions has the same conductivity type as the epitaxial layer portions of the other island-like regions, but has a different film quality.
次に本発明を実施例について説明する。Next, the present invention will be explained with reference to examples.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
図において、第１のトランジスタ１０１と第２のトラン
ジスタ２０１は、ｐ型シリコン基板１１及びｐ型分離領
域１３，１３．１３とｎ型エピタキシャル層部１５．２
５との間で形成されたｐｎ接合によシ互に電気的に分離
された島状ｎ型エピタキシャル層内に形成されている。In the figure, a first transistor 101 and a second transistor 201 include a p-type silicon substrate 11, p-type isolation regions 13, 13.13, and an n-type epitaxial layer portion 15.2.
5 is formed in an island-like n-type epitaxial layer electrically isolated from each other by a pn junction formed between the two layers.
トランジスタ１０１および２０１はコレクタ領ｊｉｌｌ
！１５，２５、ペース領域１６．２６、工に、夕領域１
７．２７及びその外ｉ電極、さらにその間に設置された
絶縁膜１４からなっている。さらに、コレクタ抵抗を下
げるためＯｎ十型埋設領域１２，２２を含んでいる。Transistors 101 and 201 are collector regions
! 15, 25, pace area 16.26, engineering, evening area 1
7.27, an i-electrode, and an insulating film 14 disposed between them. Furthermore, it includes On-type buried regions 12 and 22 to lower the collector resistance.
又、第１のトランジスタ１０１のエピタキシャル層部即
ちコレクタ領域１５の濃度は、第２のトランジスタ１０
２のエピタキシャル層部、即ちコレクタ領域２５の濃度
より低くなっている。シ九がりて、第１のトランジスタ
１０１は第２のトランジスタ２０１に比べて各領域の面
積、形状が全く同じでも、コレクタ抵抗は大キく、ベー
ス・コレクタ接合容量は小さく、その接合の耐圧は大き
くなる。即ち、＃１ぼ同じ面積、形状を保ちながら、異
なる特性のトランジスタを実現でき九ことになる。Further, the concentration of the epitaxial layer portion, that is, the collector region 15 of the first transistor 101 is the same as that of the second transistor 10.
The concentration is lower than that of the epitaxial layer portion 2 of No. 2, that is, the collector region 25. By comparison, even though the area and shape of each region of the first transistor 101 are exactly the same as those of the second transistor 201, the collector resistance is larger, the base-collector junction capacitance is smaller, and the breakdown voltage of the junction is smaller. growing. In other words, transistors with different characteristics can be realized while maintaining the same area and shape as #1.
第２図は本発明の第２の実施例である。第１のトランジ
スタ２０１と第２のトランジスタ２０２は、ｐ型シリコ
ン基板１１及び埋設酸化物２３゜２３．２３とｎ型エピ
タキシャル層部３５．４５との間で形成されたｐｎ接合
及び酸化物により互に電気的に分離された島状ｎ型エピ
タキシャル層部内に形成されている。各トランジスタは
ｎ 型埋設領緘３２，４２とコレクタ領域３５，４５、
ペース領域３６，４６、エミッタ領ｌｌＲ３７，４７及
び外部電極さらにその間に設置された絶縁Ｍ１４からな
っている６本実施例も第１の実施例同様、第１のトラン
ジスタ２０１のコレクタ領域３５の濃度カ第２のトラン
ジスタ２０２のコレクタ領域４５の濃度より低い為、異
なるトランジスタが実現されている。FIG. 2 shows a second embodiment of the invention. The first transistor 201 and the second transistor 202 are connected to each other by a pn junction and an oxide formed between the p-type silicon substrate 11, the buried oxide 23.23, and the n-type epitaxial layer 35.45. It is formed within an island-shaped n-type epitaxial layer section electrically isolated from the other regions. Each transistor has an n-type buried region 32, 42 and a collector region 35, 45,
Similarly to the first embodiment, the six embodiments, which are composed of space regions 36, 46, emitter regions 11R37, 47, external electrodes, and an insulator M14 installed between them, have a concentration cap of the collector region 35 of the first transistor 201. Since the concentration is lower than that of the collector region 45 of the second transistor 202, a different transistor is realized.
第３図は第３の実施例の断面図である０本実施例は、第
１の実施例と類似しているが、第２のトランジスタ３０
２のエピタキシャル層部の高濃度部分が、その厚さの一
部にのみわたっており、残９０部分は、第１のＦランラ
スタ３０１のエピタキシャル層部と同じ低濃度部分圧な
っているところに違いがある。トランジスタの特性では
、上記菖１と第２の実施例と殆ど差が生じ表いものであ
る。同様な類似実施例は第２の実施例についても可能で
ある。FIG. 3 is a cross-sectional view of a third embodiment. This embodiment is similar to the first embodiment, but with a second transistor 30.
The difference is that the high concentration portion of the epitaxial layer portion of No. 2 covers only a part of its thickness, and the remaining 90 portions have the same low concentration partial pressure as the epitaxial layer portion of the first F run raster 301. There is. In terms of transistor characteristics, there is almost no difference between the above-mentioned Iris 1 and the second embodiment. Similar analogous embodiments are also possible for the second embodiment.
以上本発明の実施例について説明して来たが、異なる膜
質のエピタキシャル層部を実現する為には、上記実施例
の濃度を変える方法以外に、不純物の種類を変える方法
、及び両者を組み合わせる方法等がある。The embodiments of the present invention have been described above, but in order to realize epitaxial layer portions with different film qualities, in addition to the method of changing the concentration in the above embodiments, there is a method of changing the type of impurity, and a method of combining both. etc.
第１図、第２図、第３図はそれぞれ本発明の第１実施例
、第２実施例、第３実施例の断面図である。
１１・・・・・・ｐ型基板、１２，２２，３２，４２゜
５２、．６２・・・・・・Ｎ型埋設領域、１３・・・・
・・ｐ型分離領域、１４・・・・・・表面絶縁膜、１５
．２５，３５゜４５．５５，６５・・・・・・コレクタ
領域、１６，２６゜３６．４６．５６．６６・・・・・
・ペース領域、１７゜２７．３７，４ワ、５７．６７・
・・・・・工電ツタ領域、２３０１００１．埋設酸化物
、１０１，２０１，３０１・・・、・・第１トランジス
タ、１０２，２０２，３０２・・・・・・第２トランジ
スタ。1, 2, and 3 are sectional views of a first embodiment, a second embodiment, and a third embodiment of the present invention, respectively. 11...p-type substrate, 12, 22, 32, 42°52, . 62...N type buried area, 13...
...p-type isolation region, 14...surface insulating film, 15
．． 25, 35° 45.55, 65... Collector area, 16, 26° 36.46.56.66...
・Pace area, 17°27.37, 4W, 57.67・
...Kouden Tsuta Area, 2301001. Buried oxide, 101, 201, 301..., first transistor, 102, 202, 302..., second transistor.
Claims (1)
他と電気的に分離された複数の島状領域が形成され、そ
れ゛ぞれの島状領域に回路素子が形成されている半導体
装置において、前記複数の島状領域のうちの少くとも一
つの島状領域のエピタキシャル層部が他の島状領域のエ
ピタキシャル層部と同じ導電型でかつ異なる膜質で構成
されていることを特徴とする半導体装置。In a semiconductor device in which a plurality of island-like regions electrically isolated from each other are formed in a semiconductor substrate having an epitaxial layer on the surface side, and a circuit element is formed in each island-like region, the plurality of A semiconductor device characterized in that an epitaxial layer portion of at least one of the island-like regions has the same conductivity type as the epitaxial layer portions of the other island-like regions, but has a different film quality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111946A JPS5814564A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56111946A JPS5814564A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5814564A true JPS5814564A (en) | 1983-01-27 |
Family
ID=14574105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56111946A Pending JPS5814564A (en) | 1981-07-17 | 1981-07-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5814564A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6977426B1 (en) * | 1995-12-12 | 2005-12-20 | Sony Corporation | Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5028786A (en) * | 1973-07-13 | 1975-03-24 | ||
| JPS55146960A (en) * | 1979-05-02 | 1980-11-15 | Hitachi Ltd | Manufacture of integrated circuit device |
-
1981
- 1981-07-17 JP JP56111946A patent/JPS5814564A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5028786A (en) * | 1973-07-13 | 1975-03-24 | ||
| JPS55146960A (en) * | 1979-05-02 | 1980-11-15 | Hitachi Ltd | Manufacture of integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6977426B1 (en) * | 1995-12-12 | 2005-12-20 | Sony Corporation | Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate |
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