JPS58145217A - Digital filter - Google Patents

Abstract

PURPOSE:To make the diagnosis of failure accurately without using a special device, by providing a registor storing digital data for test and transferring it to a CPU as required. CONSTITUTION:A digital filter 100 is connected to a CPU300. When an FF101 is set, i.e. in the test mode, a selector 103 outputs as output of a register 102, i.e. digital data for test transferred from the CPU300 to an operation section 104 selectively. Further, a control circuit 107 permits the filter processing for one period's share when an FF106 is set for the operation section 104. Thus, the operation section 104 performs the filter processing and stores the result of processing to a data buffer 105. This content is transferred to the CPU300 as required for the diagnosis of failure. Thus, the diagnosis of failure is made accurately without using a special device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital filter that filters sampled digital data periodically provided from an analog/digital conversion circuit.

[Technical background of the invention and its problems] Generally, this type of digital filter 1o is constructed using an analog/digital conversion circuit (hereinafter referred to as ADC) as shown in FIG.
The sampling digital data DATAADO provided periodically from the processor f (hereinafter referred to as
30 (referred to as CPU). Then, CPUJo performs various processing using the data transferred from digital filter 10. In this case, if the digital filter lO is malfunctioning, the CPUJO
An error occurs in the processing results. Therefore, it is necessary to diagnose whether or not the digital filter 10 is operating properly as necessary, and to accurately understand the state of the digital filter 10. For this purpose, a digital no filter lO
It is necessary to perform a failure diagnosis by applying a predetermined test pattern to the digital filter 10 and comparing the filter processing result of the digital filter 10 with respect to this test pattern with predicted correct data. Conventionally, in order to provide a test pattern to the digital filter 104, a dedicated test pattern generator is provided in place of the IT ADCXO, and this test pattern generator generates a test pattern at a constant cycle. Means to lead to digital filter IO at constant lI@ period.

Or +21 ADC! Means for supplying an analog test pattern as a 00A power signal to the mu DCjj and guiding the converted output of the mu DC 20 to the digital filter 101.

was there.

However, since the above method (11) requires dedicated test pattern generation and power reduction, the configuration is complicated, and even for the same analog test pattern, the output of DCJ# is not constant, so it is not accurate. Failure diagnosis could not be performed.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to:
In the test mode, each time the test digital data (digital test pattern) necessary for fault determination is received from the CPU (processing unit), which is the output light of the filter processing result, this data is filtered, and the result is It is an object of the present invention to provide a digital filter that can be transferred to the CPU as needed, and thereby allows fault diagnosis to be performed accurately from the CPU without using special equipment.

[Summary of the Invention] A first flip-flop for mode designation indicating normal mode/test mode, and a CPU (processing unit) that outputs light as a result of filtering when the first flip-flop indicates test mode. A register in which the test digital data transferred from
a selector for selectively outputting sampling digital data periodically given from a DC (analog/digital conversion circuit) to the arithmetic unit when the normal mode is indicated by flip 70; and a selector for selectively outputting the test digital data from the CPU. When the 27th lip-flop is set when the 27th flip-flop is transferred and the test mode is indicated by the first flip-flop, the
The configuration includes a control circuit that allows filter processing for a period, resets the 27th lip-flop, and requests transfer of the next test digital data to the upper CPU 4, thereby performing filter processing. The result can be transferred to the CPU.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 2, 100 is a digital filter of the present invention;
00 is a DC (analog/digital converter) that periodically supplies sampled digital data DATAADO to this digital fill loop, and Joo is a C
It is a PU (processing unit). The digital filter 100 is connected to an input/output interface (not shown) of the CPU 5oo as one of the input/output devices. In the digital filter 10Dl, 1o1 is a first flip-flop (hereinafter referred to as F/F) for mode setting indicating normal mode/test mode. F/F 7o7jtCP
It is set or reset by the -xq command (command) of U5oo6>, etc., and indicates the test mode of the digital filter 1oo in the set state, and also indicates the normal mode in the reset state. 102 is test digital data (digital test pattern) DATA transferred from the CPU5Oo in the test mode.
This is a register (hereinafter referred to as RIG) in which the OPU is held. In the actual IIafQ, the test digital data DATA CPU is held. The control signal CNT is set so that the data DATAOPυ is C
After the output from PUjl)1), C
PUJI) (This is what is output from l.

103 is a selector. Selector 10M is hoczo
o output (sampling digital data DATmu ADO
) or the output of REGtOx (test digital data DATACPU) is selected depending on the state of y/yto1. Reference numeral 104 denotes an arithmetic unit that performs arithmetic operations using the selected output of the selector 103 and performs well-known filter processing.

However, the calculation unit 104 is configured to perform either normal continuous filter processing or filter processing for one cycle under the control of the control circuit 101, which will be described later. Reference numeral 105 denotes a data buffer in which filter processing results of the calculation unit 104 are sequentially stored. The contents of the data buffer 105 are transferred to the CPU 5G in response to an output request from the digital filter 100 (not shown) or an input request from the CPU 5on.

106 is a 27th lip flop (hereinafter referred to as F/F). F/1P10fr is set by control signal CNT to indicate test digital data DATA CPU transfer from CPU''-J00.

104 is a control circuit. The control circuit 101 is v/Flo
Monitor z and toe, and if p/r J OJ is in the set rod and F/F J 0 & is set,
Operation [5 Allow filter processing for one station period for JO4. Then, the control circuit xor resets the F/F J o y and sends a request signal RIQ requesting the CPU 300 to transfer the next test digital data DATAcPU to cpuso.

It is designed to output to . Furthermore, when F/FIO1 is in the cent state and F/110# is in the reset state, the control path 10F causes the filter processing of the calculation unit 104 to wait. Further, the control circuit 10F releases control over the calculation unit 104 when the F/Flet is in the reset state. As a result, the calculation unit 104 performs normal continuous filter processing (operation in normal mode).

Next, the operation of the configuration shown in FIG. 2 will be explained. First, F/F"1
The case where 01 is the reset state, that is, the FlFzot number indicates the normal mode will be explained. In this case, the selector JOj is set according to the reset state of the F/FIOI.

The output of the ADC 20), that is, the output of the ADC 20), is applied to the calculation unit 1.
Selectively output to 04. When the F/1101 is in the reset state, the control circuit 1071 releases control over the calculation unit 104. Therefore, the arithmetic unit 104 uses the selector 11
Filter processing is repeatedly performed at a constant cycle using sampling digital data DATA Do periodically provided from DCxoe via 1M. The filtering results of the arithmetic unit 104 are sequentially sent to the data buffer 105 at regular intervals.
is stored in When the processing results for a predetermined period are stored in the data buffer 106, an output request is issued to the CPU 100 from a control section (not shown) in the digital filter 100.

Then, by giving approval to this request from cpusoo, the contents of the data buffer 101 are transferred to the CPU.
Transferred to l0e.

Next, a case will be described in which F/Ftot is set by a command from the CPU 300 and the test mode is indicated. cpuzoo is the F in the digital filter 100 in order to diagnose the failure of the digital filter ioo.
/F 101 is set, data of a predetermined test pattern, ie, test digital data DATAcpU, is transferred to the digital filter 100 as sampling data of the digital filter 1000. Next, the CPU j 00 outputs a control signal CNT indicating transfer of the test digital data DATACPH to the digital red filter 100. However, the above test digital data DmuTAcpυ
is REG7 at the timing of the above control signal CNT.
It is held at 02. In addition, the control signal CNT
F/F1ets is cented by.

When the F/FZ6Z is in the cent-like layer, that is, in the test mode, the selector 10M selects the output of RIGJoJ, that is, CP
Test digital data D transferred from UJIoo
Selectively output A T A CPU to the calculation unit 104 〇 On the other hand, when the F/F J a t is in the set state, the control circuit 101 outputs the output to the calculation unit 104 when 17210g is set as described above. Allow filter processing for one period. From this, the calculation unit 104 uses the selector tOS.
Test digital data selected by
A Filter processing for the l#l1 period is performed using QPU. The filter processing result of operation w6104 is stored in data buffer 105.

When the control circuit 10'l performs filter processing for one station period on the calculation unit 1f) 4 as described above, the F/F J
o- is reset and requests 1cePUJoo to transfer the next test digital data DATAQPU. Then, in response to this request, the next test digital data DATAOP is transferred from the CPU3oO.
U is held in RF, , G10:I as in the case described above. At this time, y/Fruit is set again. As a result, the arithmetic unit 104 is permitted by the control circuit 107/ to perform filter processing for the next cycle, and performs filter processing using the next test digital data DATAcpU.

By the way, when the CPU 100 is in a so-called busy state in which it is executing various processes, the calculation 5104 is 1.
Even after completing the filter processing for the period, the CPU 300
The next test digital data DATAOPU may not be transferred. However, in this embodiment, since F/FIO- is not set unless the next test digital data DATAcpU is transferred, the control circuit 10
7 does not permit the calculation unit 104 to perform filter processing for the next cycle, and therefore there is no fear that the calculation unit 104 will repeatedly perform filter processing on the same test digital data DATAcpU.

In this way, the calculation unit 104 in the digital filter l0eJ calculates the data oArA every time the predetermined test digital data DATAcPU is transferred from the CPU l0e.
Filter processing using opu can be performed correctly. The filter processing results of the calculation unit 104 are sequentially stored in the data buffer 106. After transferring a certain number of test digital data DATAcpg, the CPU 300 issues a data input request to the digital filter 100. The contents of the data buffer 10'l are stored in response to an input request from the CPU 3oo from the control unit number (not shown).
Transferred to oo. The CPU 100 compares the digital filter 000 processing result corresponding to the certain number of test digital data DATAOPU transferred from the digital filter 00 with the correct data calculated in advance, and based on this comparison result, the digital - Perform a failure diagnosis of the filter 100.

[Effects of the Invention] As described above in detail, according to the digital filter of the present invention, the output light of the filter processing results in 6 CPUs (processing value f).
Each time it receives test digital data necessary for fault diagnosis from the
Since the results of step 7 can be transferred to the CPU as necessary, failure diagnosis of the digital filter can be accurately performed from the CPU without using any special equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram of the present invention.
*It is a block diagram showing an example. No. 10.100...Digital filter, 20°200
...Analog/digital conversion circuit (ADCχso,s
oo... Processing unit I (CPU), 101... First flip 70 block (F/F), x o z... Register (RIG), 103... Selector, 104... Arithmetic unit, 106...Second flip-flop (F/IF)
, lay...control circuit. Client's agent Patent attorney Takehiko Suzue, Figure 1

Claims (2)

[Claims] (1) In a digital filter equipped with an arithmetic unit that filters sampling digital data periodically provided from an analog/digital conversion circuit, a test is performed using a 17th flip-flop indicating normal mode/test mode and this first flip-flop. When the mode is indicated, there is a register that holds the test digital data transferred from the processing device connected to the digital filter, and the contents held in this register or given from the analog/digital conversion circuit described above. A selector selectively outputs one of the sampling digital data as digital data to be processed to the arithmetic unit according to the state of the first flip 70, and the test digital data is transferred from the processing device. The 27th lip flop that is set when the
When the flip-flop is in the set state and the test mode is indicated by the first flip-flop, the arithmetic unit is allowed to perform filter processing for one period, and the 27th flip-flop is reset, and the queen processor is activated. A digital filter configured to be transferred to a next test digital device. (2) The digital filter according to claim 1, wherein the first flip 70 is configured to indicate a normal mode or a test mode depending on a command number from the processing device. . (31) When the normal mode is indicated by the #Il flip 70 amplifier l, the control circuit allows continuous filter geography to the arithmetic unit. Or the digital filter described in Section 2.