JPS58144989A - Electronic postage calculater with redundant memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic accounting systems, and more particularly to an electronic postage meter having a microprocessor-controlled electronic accounting device with non-volatile random access memory.

An electronic postage meter having an accounting device with a microprocessor and a non-volatile memory for storing accounting data is disclosed, for example, in US patent application Ser. No. 089.413. In this system, accounting data is stored in and retrieved from random access memory through common address and data lines of the microcomputer system. Although in most cases it can be guaranteed that the accounting data stored in memory is valid, it is also true that certain conditions can occur that can cause undetected errors in the data.

As a method to solve this problem, a method using redundant memory has been proposed. Accordingly, the postage meter's microprocessor program includes a shark routine for comparing the data stored in the redundant memories, thereby providing an error indication if the data stored in the two memories differ.

Although the above technology improves the reliability of stored data,
It is also true that even with this type of redundant system there are certain conditions under which error determination cannot be made.

Of course, it must be emphasized that in postage meters it is important to obtain accounting data with a high degree of reliability.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an electronic postage meter with redundant memory in a non-volatile accounting memory in which the possibility of undetected error conditions is minimized.

A brief explanation will be given below. According to one aspect of the invention,
Redundant non-volatile memory is located in the electronic postage meter accounting device. The accounting device has a microprocessor controlled to redundantly store accounting data in two memories. To minimize the possibility of undetected errors, the two redundant memories are interconnected with the microprocessor, or microcomputer bus, via completely independent sets of data and address lines. There is. For example, various error conditions such as shorting of a pair of address lines will not result in incorrect addressing of both memories. Therefore, under such conditions, even if a pair of address lines are short-circuited, the same data will not be stored in both memories, and an error condition will be detected when the stored data is compared.

According to another embodiment of the invention, corresponding data is redundantly applied to the redundant memory at different times. This function is performed by applying data to two memories serially and separately. Also, if the data transferred at any point in time with respect to the two memories corresponds to different information, data can be applied to the two memories simultaneously or retrieved from the two memories. As a result, instantaneous transitions in the transmission line cannot affect the corresponding data stored in the two memories in the same way. Accordingly, this system minimizes the possibility of undetectable and/or uncorrectable errors arising from transitions.

According to yet another embodiment of the invention, redundant microprocessors for controlling two memories are used to increase redundancy in the accounting system.

To further minimize the possibility of postage being printed without accounting, the microprocessor's program is directed to periodic testing of various critical parameters within the microprocessor as part of its main routine. It should be noted that only this test routine is stopped as necessary during conventional postage printing operations, such as printing postage and accounting for it. As a result, the postage meter routine allows such /ξ millimeter continuous testing so that the postage meter can be deactivated as soon as a condition exists that compromises the integrity of the accounting data. By periodically checking for errors, not only physical parameters such as the position of various mechanical elements can be tested, but also a comparison of the data stored in the two memories is carried out. Furthermore, a control phase check is also performed to determine whether the data stored in each memory follows a predetermined relationship.

The present invention will be described below with reference to the drawings.

First, let's talk about Figure 1. FIG. 1 shows an electronic accounting system that may be used in an electronic postage meter. This system 4
The system is comprised of a central processing unit 10 such as a microprocessor, and a read-only memory IJ (ROM) 11 that stores programs for operating the system. The central processing unit 10 is coupled to one or more peripheral devices, such as a printing device 12 and a controller 13 of an electronic postage meter, such as that disclosed in US patent application Ser. No. 089.413. In the system of FIG. 1, a stationary housing 14 encloses various system components, such as a central processing unit 10 and a printing device 12. In the system of FIG.

As a result, in order to enable two-way communication between the central processing unit 10 and the external control device 1, it is necessary to provide a port between these devices.

These ports are preferably in the form of a pair of unidirectional transmission paths with optocouplers 15 and 16 disposed in the fixed housing. This is so that when an electrical potential is applied to the accounting device, it cannot be applied without leaving traces that would indicate a possible attempt to damage the accounting device. The optocoupler preferably provides two-way serial intercommunication between devices that is processed bit by bit in order to minimize the number of ports required in the housing.

Further, as discussed in U.S. Pat. It is desirable to have this done.

It is preferable that these optocouplers perform serial two-way transmission of one bit at a time.

The same can be said of the control device, but if necessary, the Mark-1 device may include an independent microprocessor. This allows multiple dedicated microprocessor systems to be used. This not only increases the safety of the system, but also increases its reliability by limiting the required tasks of each microprocessor to specific portions of the overall operation of the system.

For example, the likelihood that conflicting programs will be needed is greatly reduced.

As shown in FIG. 1, a pair of random access memories (RAMs) are also disposed within the fixed storage. Random access memories 20 and 21 are preferably non-volatile memories of conventional nature so that accounting data is stored without loss even if external power to the system is lost. As an example,
It can be a type of random access memory using battery backup, EAROM or EEPROM.

According to the invention, random access memory 20 is connected to central processing unit 10 via a plurality of address lines 22 and a plurality of data lines 2.

Random access memory is connected to multiple address lines 24.
and the central processing unit 1 via another plurality of data lines 25.
0. According to the invention, both the address lines and the data lines coupled to the random access memory need to be different. For example, address line A
0-A7 have the characteristics of a conventional microprocessor system and are coupled to random access memory 20, whereas address lines CO-C7 are coupled to random access memory 20. Similarly, the conventional data line BO
~B6 to random access memory 20. Note that the data lines D4 to D7 are coupled to the random access memory 21.

In accounting systems that require both safety and reliability, it is desirable to have redundancy. Although using the same address lines, a certain degree of redundancy is obtained if the random access memory is connected to the central processing unit via separate data lines.

In such a system, these two random access memories may store the same data via their independent data lines and under the control of their respective chip enable signals at the same time or at separate times; These random access memories can be searched. Although in many instances such devices are capable of detecting errors when comparing data in two memories, in practice there remains a possibility that undetected errors exist. For example, if two of the above address lines are inadvertently shorted, either within the microprocessor itself or externally, the two random access memories will store the same error data, so the data will not be stored in these two memories. The error condition will not be discovered by comparing the existing data.

The present invention solves the above problem by using completely different sets of address lines as the address lines of the address bus for addressing the two random access memories. Of course, it is preferable that the number of address lines and the number of data lines connected to each random access memory be the same. Thus, even if, for example, two address lines of the system are shorted, the data stored in the two memories is unlikely to be the same, greatly increasing the reliability of the system in detecting errors.

Although two random access memories can be simultaneously addressed to store or retrieve the same information using separate address lines, it is true that errors may occur that cannot be detected or corrected. For example, transients on the busbars may similarly interfere with simultaneously transmitted data. Thus, as shown in FIG. 2, according to another feature of the invention, two memories are addressed sequentially for the same data. for example,
All serial bytes of a message are first stored in the first memory,
That is, it can be applied to or received from memory 1. After transferring this message to or from the first memory, the same message is transferred to or from the second memory. It is, of course, clear that the term "byte" herein refers to a length of data equal to the number of data lines connected to each memory.

As shown in Figure 6, each memory may be updated or read simultaneously, with different data being transferred to or from each memory, in order to reduce the time required to update or read the memories. I can do it.

FIGS. 2 and 3 illustrate two methods for minimizing the occurrence of undetectable errors that result, for example, from the occurrence of transient pulses. It is clear that the same interference cannot be applied to sequentially transmitted data.

According to yet another embodiment of the invention, data can be stored in two memory systems in different formats. For example, in order to further minimize the occurrence of errors that cannot be detected by comparing data stored in two memories,
Data stored in one or both of these memories can be encoded. For example, as shown in FIG. 41, a loader/decoder 30 can be used to encode and decode data stored in random access memory 20, and to apply data to data bus 26 and to apply data to data bus 26.
Receive data from 3. The loader/decoder 31 may be arbitrarily arranged to encode and decode data in the random access memory. If such an additional coder/decoder is used, it is preferable to use a different coding than that of loader/decoder 30.

Of course, it is clear that the microprocessor program will have appropriate subroutines to determine which memory has a greater chance of correctness when a comparison of the data indicates a mismatch. Additionally, routines are provided to handle when the system is not capable of determining which data entries are error-free, and error indications are provided to prevent further operation of the system. .

In the embodiment of the invention shown in FIGS. 2 and 3, the two memories are addressed, for example, under the control of a fixed program responsive to fixed conditions of the system. As a result, there necessarily exists a fixed relationship between the addressing times of two memories. Another modification would be to make each memory respond differently to a fixed condition if separate memory units are provided. For example, if the accounting systems are interconnected to form a postage meter as shown in FIG. 1, two memories may be separate for each printer setting feedback. Note that at this time, a priority subroutine is provided for cross-checking, that is, for comparing data stored in two memories. The independent controller may take the form of a memory controller, for example. By enabling the two memory units to operate more independently of each other in this manner, the chances of further error-free operation are greatly increased.

To ensure proper operation and thus maintain the integrity of stored accounting information, the electronic postage meter includes a sensor 50, shown coupled to the central processing unit in FIG. A plurality of sensors such as 51 and 52 are arranged. These sensors are used to check a number of conditions within the fare meter. The conditions to be checked include the position of the shutter per block of the fare meter, the positions of various interposers that control the operation of the fare meter, and conditions such as temperature and humidity. U.S. Patent No. 5,978,457 (case
In non-electronic postage meters of the type that utilizes a microprocessor in the control unit, such as that disclosed in US Pat. It will be done. By way of example, the positions of the various shutter bars and interposers are also determined by software routines that are initiated by various externally generated conditions, such as, for example, manual control actions to initiate printing of postage. The same is true for error checking routines for checking additional conditions such as the correctness of the data stored in memory, but an error checking routine for checking such a sensor would be
It is called only when specifically requested in response to an external stimulus. Thus, even if a condition occurs in the amount of movement of the postage meter that ultimately causes it to stop working, i.e., on the next request for printing postage,
The toll meter will still appear to be operational and will not be discovered.

According to a further feature of the invention, a program of the microprocessor performs postage checking of the registers of the random access memory as well as checking of various sensors, which may be optical switches, as well as checking of all other critical data indicators. This is done at regular intervals during the meter's operation, and these parameters are not simply checked at the start of the meter without external stimulation. Such periodic checks further increase the likelihood of error-free operation. In other words, the main routine of the postage meter, to which it always returns after completion of a postage printing operation, for example, includes a software subroutine that periodically checks critical parameters. This critical parameter is:
The proper arrangement of the mechanical elements in the meter, the proper comparison of the data in memory, and the validity of the data based on the control phase data. In this way, physical disturbances in the fixity of the housing are detected by additionally and appropriately periodically checking the installed cells.

As shown in FIG. 5, in order to achieve the above purpose, cells 50, 51. and 52 are connected to set a plurality of stages of the shift register 55.

Of course, it is understood that the number of such sensors may be greater than the three in this embodiment. Shift register 55 is coupled to addresses that are read by central processing unit 10 at predetermined times during the main program. An encoded bit pattern is provided in the read-only memory 11 corresponding to a valid error-free condition of the sensor. At times during the program when the sensor is tested, the shift register is stored in read-only memory 1 under the control of the central processing unit.
Shift out the existing bit pattern for comparison with the bit pattern stored in 1. Thus, since the state of the various sensors of the toll meter can be determined continuously, the toll meter can be de-energized as soon as a condition exists that compromises the integrity of the toll meter.

Of course, the shift registers can be shifted under microprocessor control by conventional clock sources in the system. Also, since the shift register can be preprogrammed according to a predetermined unique pattern, the output of the shift register can be compared to a predetermined "good" condition.

According to this embodiment of the invention, the information obtained from the 8-bit ξ turncode or the 16-bit turncode 8 provides a very high degree of sophistication for determining appropriate error checking for diagnostic purposes using signature analysis techniques. giving.

This type of error checking can serve various system limitations for automatic diagnostic possible error correction.

As mentioned above, in the system of FIG. 1, central processing unit 10 . A dedicated system of accounting equipment can be used, including a read-only memory 11 and random access memories 2o and 21. According to another embodiment of the invention, printing device 12 further incorporates random access memory 60 and/or controller 16 includes non-volatile random access memory 61.

As shown in FIG.
tt system non-volatile random access memory 20.
21 are mutually independent microprocessors 60 and 61
are interconnected. Each microprocessor has an independent read-only memory for storing operating programs for the respective microprocessor.

The same is true for the device of FIG. 1, but in the device of FIG. 6 it is clear that the read-only memory can be integrated into the same integrated circuit as the microprocessor, as can other components of the system.

Since the two microprocessors are separately controlled and have independent address lines 64 and data lines 65, the two random access memories are completely independently controlled. The two microprocessors are in separate communication with the controller 16 and the printer 12 via separate selection switches 7o and 71 addressed by the respective microprocessors 60 and 61.

As a result, each microprocessor receives signals from the printer and controller, and each microprocessor is also capable of transmitting messages. Additionally, data processed by the two microprocessors is compared by a data latch 72 that can be controlled by either microprocessor.

In the apparatus of FIG. 6, input data received from, for example, a keyboard "73 or other peripheral device coupled to the control device 16 is transmitted to the optocups 215 and 16 and the selection switch 70.
and 71 to the two microprocessor systems. Also, in response to an interrupt signal, data is
input into one microprocessor. The two microprocessors respond to the input information and perform the necessary accounting procedures. This procedure is performed independently of each other for the data stored in each random access memory. Accounting data is exchanged and compared by the two microprocessor programs, for example in the form of contention via data latches 72. By programming two microprocessors, for example, only one of the two microprocessors controls display device 75 coupled to control device 16 and/or controls printer 12 . Of course, redundant control can also be used so that the output functions of the two microprocessors need to be shared in order to control the printer function or to control the display device. This function can be used, for example, in US patent applications.
This can be done by the method described in No. 89.413. That is, a pair of series transistors are separately controlled by two microprocessors, thereby controlling the common output of the series transistors in a desired manner. Of course, it is obvious that other methods may be used to achieve this objective.The arrangement of Figure 6 increases the redundancy of the system so that even if the microprocessor fails, the meter cannot be disabled. The occurrence of desired error conditions can be determined with a high degree of reliability.

In the system of FIG. 6, the printer 12 is more fully illustrated with a microprocessor 80 coupled to optocouplers 17 and 18 controlling a print setter 81. Print setter 81 is printer 8
2, and this set of print wheels is fed back 9 feet to microprocessor 80 via feedback path 86. From this feedback, the printer determines whether an error has occurred in the print wheel setting and disables the meter in that setting. This feedback setting is
0 to optocouplers 17 and 18, which cause the two microprocessors of the accounting system to respond separately to the feedback signal and account for the charges to be printed.

Of course, it will be apparent that in the disclosed system of the present invention, appropriate control lines are connected and disposed in a conventional manner to the microprocessor and random access memory to control these systems.

The functionality of disabling the toll meter in the described embodiment of the invention may be implemented by inhibiting the operation of the mechanical elements of the toll meter under program control. Also, if there is an error requesting that the meter be disabled, the microprocessor routine executes an endless loop. Errors that do not require meter disablement are displayed by a display 73 coupled to the external controller and under microprocessor control.

It goes without saying that other types of memory may be used instead of RAM, such as serial memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of an electronic postage meter according to the invention; FIG. 2 is a time diagram illustrating the sequence of addressing redundant memory according to another embodiment of the invention; FIG. 4 is a block diagram of a portion of the system of FIG. 1; and FIG. 5 is a time diagram illustrating an alternative order for addressing redundant memory according to the invention; Block Diagram of Some Other Modifications FIG. 6 is a block diagram of another modification according to the present invention. 12.82... Printing device, 20.21.
...Random access memo 1c 22...
...address line. 23.25...Data line, 50,51.
52...Sensor, 55...Register, 83...Feedback means. Patent applicant Pitney Bowes

Claims (1)

[Scope of Claims] (1) A microprocessor connected to a plurality of address lines, a plurality of data lines and a control line means, and a random access memory means connected to said address lines and data lines and said control line means. and in an electronic postage meter system for storing data in and reading data from said memory means under control of said microprocessor, said random access memory means each being connected to a separate set of said address lines. and a first random access memory and a second random access memory connected to separate sets of said data lines, such that data is connected to said first random access memory and said second random access memory regardless of any common interconnection. an electronic postage meter system, characterized in that the electronic postage meter is transmitted to and from a memory and a second random access memory; (2) for storing a postage meter programmer for controlling said microprocessor; Claim 1, further comprising fixed storage means, wherein the program addresses the first random access memory and the second random access memory serially in time to transfer the same data. The electronic postage meter system according to (3) further comprising fixed storage means having a postage meter program for controlling the microprocessor, the program overlapping the first random access memory and the second random access memory. transferring the same data to and from the first random access memory and the second random access memory, respectively, addressing in time, whereby both of the random access memories Claim 1, characterized in that the same data is transferred to and from the first random access memory and the second random access memory at different times while being addressed in an addressing cycle. The electronic postage meter system of paragraph 1. (4) a microprocessor comprising a plurality of address lines and a plurality of data lines and control line means and a random access memory connected to said address line, data line and control line means. an electronic postage meter having means for transferring data between said random access memory means and a microprocessor, said printer being connected to be controlled by said microprocessor and said printer means for said microprocessor; In an electronic postage meter having feedback means for notifying the setting of the first random means for updating accounting data stored in each of the access memory and the second random access memory; a first accounting register and a second accounting register connected to be controlled separately by a processor;
an accounting register, provided that the first microprocessor and the second microprocessor are connected to each other and have a program for separately updating their respective accounting registers and accounting for the printing of charges by the charge meter; To compare the accounting results in the setter and the second microprocessor, the first accounting register and the second accounting register, and the first accounting register and the second accounting register, and to prohibit the use of the postage meter if there is no match. An electronic postage meter characterized in that it includes means. 6. The electronic postage meter of claim 5, wherein the first and second microprocessor routines store data in their respective accounting memories with different coding. 7. The electronic postage meter of claim 5, wherein the printing device includes a separate microprocessor having a postage printing program for controlling printing of the postage meter. (8) An electronic postage meter, comprising a microprocessor;
an electronic postage meter having register means coupled to said microprocessor for storing postage accounting data, and a plurality of sensors for sensing operating conditions of said postage meter; An electronic postage meter characterized in that it has a software routine for periodically checking the sensor, and means responsive to said software routine for indicating an error condition and responsive to the absence of a unique pattern. (9) An address bus having a plurality of address lines, a data bus having a plurality of data lines, a control bus having a plurality of control lines, connected to each of the address lines of the address bus and the data lines of the data bus, and the control a microprocessor coupled to a bus; and a first random access memory and a second random access memory each connected to a different line of the address bus and a different bus of the data bus and thereby separately addressed. microprocessor system. α0) A patent characterized in that the patent further includes a program memory for controlling the operation of the microprocessor, and a program for addressing the first random access memory and the second random access memory to store the same data. A microprocessor system according to claim 9. 0υ Claim 10, characterized in that said program addresses corresponding storage locations in said first memory and said second memory, and corresponding data are stored in or read out from these memories at different times. Microprocessor system as described. f121 The program transfers different data to the first
Claim characterized in that the data stored in the first memory and the second memory are stored simultaneously in non-corresponding address locations, so that a sudden error acts differently on the data stored in the first memory and the second memory. 12. The microprocessor system according to claim 11. (131) The microprocessor system according to claim 9, wherein the random memory is a nonvolatile memory. 04) In response to a difference between data stored in the first memory and the second memory, the 14. The microprocessor according to claim 13, further comprising means for inhibiting further operation of the microprocessor.