JPS6162161A - Non-volatile memory having real time and power down data memory capacity for electronic postage meter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates to electronic postage meters, and more particularly to real-time and power-down systems for electronic postage meters.
The present invention relates to a non-volatile memory (NVM) device with 11 data storage capabilities.

For example, U.S. Patent No. 3,978,457 entitled "Microcomputerized Electronic Postage Meter";
93a, No. 095, “Computer-Responsive Postage Meter J
, European Patent Application No. 80400603.9, ``Electronic Postage Meter with Improved Stability and Fault Tolerance Characteristics,'' filed May 5, 1980, U.S. Patent No. 4.3.
OL No. 507, “Electronic Postage Meter with Multiple Calculating Devices,” and pending Application No. 447, 815, “Stancia Lawn Electronic Mailing Device,” filed on December 8, 1982. A variety of electronic postage metering devices have been developed.

Generally, electronic postage meters include some form of non-volatile memory capability for storing important postage accounting information. This information includes, for example, the amount of postage remaining in the meter for subsequent printing and the total amount of postage already printed by the meter. Other forms of accounting or operational data may also be stored in non-volatile memory if desired.

However, situations occur within electronic postage meters in which information stored in non-volatile memory is lost. Any line power failure or voltage fluctuation condition may cause the microprocessor connected to the meter to operate erroneously and erase data or write parasitic data in the non-volatile memory. Erasing data or writing parasitic data within non-volatile memory results in loss of critical accounting information. Accounting data changes depending on the postage print and is not permanently stored anywhere.
There is no way to reconstruct lost accounting information.

Under such circumstances, users may suffer from loss of postage funds.

In order to minimize the possibility of loss of information stored in non-volatile memory, various approaches have been adopted to ensure the robust reliability of electronic postage meters. A microprocessor-controlled e-mail having a memory architecture comprising temporary storage memory for storing accounting data reflecting the operations of each rate meter, and non-volatile memory in which the accounting data is transferred during power-down cycles of the rate meter. A charge meter is provided from the aforementioned U.S. Pat. No. 3,978,457 and the aforementioned pending application Ser. No. 447.815.

Another approach to preserving stored accounting data is to use redundant non-volatile memory. One such redundant memory device is FrankT, Check,
Jr., Patent Application No. 343.877, filed on January 29, 1982, entitled "Electronic Postage Meter with Redundant Memory." In such redundant memory devices, two redundant non-volatile memories are interconnected at the microprocessor by means of a loop that completely separates the data and atlus lines to eliminate error conditions. Data may be provided to the memory simultaneously or sequentially at different times. Such a device minimizes the possibility of temporarily introduced undetectable and/or uncalibrated errors.

Another redundant memory device is the aforementioned Yorotsuno ξ Patent No. 8
04006'03.9. In this patent application, accounting data is stored twice during each postage meter operation, once in temporary form and once permanently, in order to minimize erasure of accounting data during microcomputer failure. specified BA of each of the two non-volatile memories in the form of
MK is written.

The aforementioned redundant memory devices help eliminate errors in the accounting data due to microcomputer failure or the presence of flash transfers. However, since these memory writes occur during each charge meter transaction, 9) during the rip cycle, critical accounting data is most likely to be transferred or transferred during most of the charge meter's operation, when the presence of parasitic signals is at its greatest. Written to non-volatile memory during noisy cycles.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile memory device for electronic postage meters that minimizes errors in stored accounting data.

Another object of the present invention is to provide a non-volatile memory device for an electronic postage meter in which accounting data is written to the local NVM during two different cycles of operation of the postage meter.

Another object of the present invention is to provide a non-volatile memory device with real-time and power-down data storage capabilities for electronic postage meters to minimize the possibility of errors in stored accounting data. be.

In summary, the present invention provides a method and related apparatus for increasing the reliability of stored accounting data that reflects the operations of electronic postage meters. The method and related apparatus include a first postage system capable of storing accounting data reflecting the operations of the postage meter;
updating the first non-volatile memory for each postage transaction in real time to provide a then-current record of accounting data for each postage transaction in progress; providing a second non-volatile memory capable of storing accounting data representative of postage meter operations during a power down cycle; providing volatile memory capable of storing accounting data representative of postage meter operations; Updating volatile memory for each postage transaction in real time to provide a then-current record of accounting data for the transaction, and updating volatile memory for each postage transaction in real time to provide a current record of accounting data for the transaction;
transferring accounting data to non-volatile memory, each step of the process and associated equipment.

DETAILED DESCRIPTION In FIG. 1, the electronic postage meter non-volatile memory device of the present invention is shown generally at 10. Preferably, the overall architecture of the electronic postage meter is based on the aforementioned pending patent application no. 4, modified as disclosed in FIG.
No. 47.815. In particular, a central processing unit 12 in the form of a microprocessor, for example a model 8085A microprocessor, has a ROM 1
It is operated under program control based on programs stored in 4. Microprocessor 12 is energized by the output of power supply circuit 16 during a power-up cycle to place the meter in operation. The microprocessor 12 is connected to a data bus 1 connected to the various fare meter elements.
Sends and receives signals via 8.

Generally, microprocessor 12 sends and receives signals to and from other electronic components 20, keyboard 22, and printer 24 to operate stepper motor and bank regulator and lens 26 to effectuate the printing of postage on documents. Each postage operation or print job is referred to as a trip cycle.

During each trip cycle, a certain amount of postage is used. Volatile random access memory 28, such as type 8155, with appropriate input and output and timing circuitry
is provided with an ascending order register (AR), an order register (DR) and an appropriate cyclic redundancy code (CRC) and a control sum. During each trip cycle, and under the control of the microprocessor 12, The descending register is decremented by the correct amount of postage used during the trip, and the ascending register is incremented by the correct amount of postage used during the trip. Thus, the AR gives the then-current total of the amount of postage used by the completion of , while DR gives the then-current total of the amount of postage remaining in the rate meter for the next use.

A first NVM 30 is also connected to data bus 18 for receiving accounting data from microprocessor 12. Preferably, it is NVM30 & 5EEQ5516A Electrically Erasable Read-Only Memory (EERQM) with an endurance of 1 million write cycles. but,
Other NVMs with high durability such as battery back C
MO3 integrated circuit chips or other similar integrated circuit chips can also be used.

Under the control of the microprocessor 12, accounting data for each postal service, AR and DRl, and other desired accounting data are stored in the NVM 30 and volatile RAM 28.
will be written to. In this way, permanent update records of accounting data are real in lffM3Q;
,4. , kept in progress in time.

A second NVM such as an ER3400MNO8 integrated circuit chip
32 is also electrically connected to the data bus 18.

Under the control of microprocessor 12, accounting data temporarily stored in RAM 28 during each meter's operation is transferred from RAM 28 upon detection of a power-down signal indicating the beginning of a power-down cycle. second N1
Written into M32.

During normal operation of the postage meter, the second NVM 32 is held in a non-write state by an output signal from the microprocessor 12 via the data bus 18. However, during a power failure (power down cycle), microprocessor 12 initiates a power down cycle routine.

Accounting data temporarily stored in volatile RAM 28 is written to be transferred to first ONVM 32 in this routine. Upon completion of the transfer of accounting data to the second N7M 32, the second NVM 32 is disabled by the power down detection circuit 34 to prevent further writes by the microprocessor 12.

Preferably, the power supply circuit 16 and the power down detection circuit 34
No. 4, issued April 24, 1984.
, 445, 198, ``Memory Protection Circuit for Electronic Postage Meter''. In response to receiving the first low power signal from power supply circuit 16 , power down detection circuit 34 performs a predetermined process to enable transfer of accounting data from RAM 28 under control of microprocessor 12 . A bias signal is provided to the second NVM 32.

The bias voltage is then removed from the second NVM 32, disabling it and preventing further writing of data from the microprocessor 12. Separately, the power supply circuit 16 and power-down detection circuit 34 are described in pending patent application no.
．． The output signal from the second microprocessor f12, of the type disclosed in ``Non-Volatile Memory Protection Circuit with Microprocessor Interaction,'' No. 971, is also electrically connected to the power-down detection circuit 36.

This detection circuit 36 is of the type disclosed in the pending application ``Data Protection Apparatus for Electronic Postage Meters Having Multiple NVMs,'' filed on the same day as this application. Power down protection circuit 36 inhibits further writing to first ONVM 3Q in response to detection of a power down condition by microprocessor 12.

A flowchart at 50 for the operation of the memory device of the present invention is shown in FIG. In view of this flowchart 50 and the apparatus 1o shown in FIG. 1, after the postage meter is powered up and before the start of a trip cycle, the meter is in its stationary stable state. In this state, if the microprocessor f12 is in a power down state or detects a stain source failure, the microprocessor 12 will write the accounting data to the second NVM 32 so that the
Immediately transfer all accounting data from 28 to the second NVM 32
Transfer to. Thereafter, the power down detection circuit 34
NVM 32 is disabled to preclude further writing of parasitic data due to erroneous operation of microprocessor 12 during the remainder of the power down cycle. RAM2
8 to the second NVM 32, when the voltages applied to the various circuit elements are decreasing towards zero volts due to unspecified and undefined bias conditions. 1 NVM 30 is in power-down protection circuit 36 for the remainder of the power-down cycle.
This prevents further writing of parasitic data due to erroneous operation of the microprocessor 12.

If no power down condition exists, microprocessor 12 waits for a trip signal indicating that a trip cycle is being initiated. When a trip exists, the accounting data in RAM 28 is updated to reflect the results of the most recent postage transaction or trip cycle. Additionally, accounting data for postage transactions is written to the fsl's NVM 30.

After writing the accounting data for the newest business to the RAM and the first NVM3Q, the microprocessor 12
looks for power down conditions. If such a condition exists, the above operation is performed and the accounting data is stored in RAM2.
8 to the second NvM32, and the first ON at one-way
Prevent further writing of data to VM 30.

If a power down condition does not exist, the microprocessor 12 stores the accounting data in the RAM 2a and the first NV.
After writing into M30, look for the trip complete signal.

In response to detection of the trip complete signal, the meter returns to its steady state, where the process described above repeats.

From the foregoing discussion, it can be seen that "permanent" storage of accounting data is carried out in real-time on a per-job basis to provide an initial accounting data file during one cycle of meter operation, i.e. during a trip cycle. "Permanent" storage of accounting data may also be used to store accounting data temporarily during another cycle of meter operation to provide a second accounting data file during a power down cycle. It is clear that the transfer from memory to "permanent" memory is provided during the power down cycle. Preferably, the second accounting data file is permanently configured during a power down cycle during a period of operation of the meter when parasitic signals are at a minimum.

The term "postage meter" refers generally to any device for printing unit values on parcels, envelopes, government or private carriers, or for other similar uses for printing unit values. For the purposes of this application, it should be understood that a species of any kind is meant. Thus, the term "postage meter" is used, but it is not used commercially as a general term for equipment used with services other than those used exclusively by the government postage and tax service. It is also known and used in For example, commercial parcel and flight services purchase and use such charges as a means of providing unit value printing and accounting for individual parcels.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the nonvolatile memory device of the present invention, and FIG. 2 shows the operation of the nonvolatile memory device of the present invention.
0 - Chart. lO: Electronic postage accounting, 12: CPU, 14
:ROM116: Power supply circuit, 18: Data bus, 20:
Other electronic elements, 22: Keyboard, 24: Printer, 2
6: Step motor, bank motor and retractor, 2
8: RAM, 30: ilCINVM, 32
: 217th) NVM, 34: Hower down detection circuit, 36: Power down retention circuit. (5 other people)

Claims (14)

[Claims] (1) In a method of increasing the reliability of stored accounting data reflecting electronic postage meter operations, the method comprises: providing a first non-volatile memory capable of storing accounting data representative of postage meter operations; updating the first non-volatile memory in real time for each postage transaction to provide a current record of accounting data for the transaction; updating accounting data representative of the postage transaction during a power down cycle of the postage meter; providing a second non-volatile memory capable of storing; providing a volatile memory capable of storing accounting data representative of postage operations; updating the volatile memory in real time to the postage meter; and transferring the accounting data from the volatile memory to a second non-volatile memory during a power down cycle of the postage meter. How to increase reliability. (2) The method of claim 1, wherein the first non-volatile memory is updated during each trip cycle of the meter. (3) The method of claim 2, wherein the first non-volatile memory has greater durability for data storage than the second non-volatile memory. (4) In claim 1, updating the first non-volatile memory under the control of a microprocessor; and transferring data to the second non-volatile memory during a power down cycle under the control of the microprocessor. , a method having the following steps. (5) A method of increasing the reliability of stored accounting data reflecting the operations of an electronic postage meter, comprising: providing a first non-volatile memory capable of storing accounting data representative of operations of the postage meter; updating the first non-volatile memory during each trip cycle of the postage meter to write accounting data therein; and providing a second non-volatile memory capable of storing accounting data representing operations of the postage meter. , and writing the accounting data into a second non-volatile memory only during power down cycles of the postage meter. (6) providing a first non-volatile memory capable of storing accounting data reflecting the operations of an electronic postage meter in a manner of increasing the reliability of stored accounting data reflecting operations of the electronic postage meter; writing accounting data to the first non-volatile memory during each postage transaction to provide a current record of accounting data for each postage transaction of the postage meter; accounting data reflecting the postage transaction can be stored; providing volatile memory; writing accounting data into volatile memory during each postage transaction to provide a current record of accounting data for each postage transaction; upon detection of a power-down signal; enabling the writing of accounting data into a second non-volatile memory and accounting data reflecting the operations of the postage meter written into the non-volatile memory during two different cycles of operation of the postage meter; In order to provide two records, accounting data residing in volatile memory is transferred to a second register upon detection of a power down signal.
A method for increasing the reliability of stored accounting data, comprising the steps of: transferring the data to a non-volatile memory; (7) In an apparatus for increasing the reliability of stored accounting data reflecting the operations of an electronic postage meter, a first non-volatile memory for storing accounting data reflecting operations of the postage meter; a volatile memory means for storing accounting data reflecting the operations of the postage meter; a second volatile memory means for storing accounting data reflecting the operations of the postage meter;
non-volatile memory means electrically connected to said first and second non-volatile memory means and said volatile memory means for storing accounting data in real time during each trip cycle of the postage meter; writing to means and said volatile memory means;
and microprocessor means for transferring accounting data stored in said volatile memory means to said second non-volatile memory means only during meter power down cycles;
A device for increasing the reliability of stored accounting data. 8. The apparatus of claim 7, wherein said first non-volatile memory is updated under control of said microprocessor means to reflect postage meter operations. (9) The device according to claim 7, wherein the first non-volatile memory has greater durability for data storage than the second non-volatile memory. (10) The device according to claim 7, wherein the first nonvolatile memory is an EEROM. (11) In an apparatus for increasing the reliability of stored accounting data reflecting the operations of an electronic postage meter, first non-volatile memory means for storing accounting data representative of operations of the postage meter; second non-volatile memory means for storing accounting data representative of a transaction, electrically connected to said first and second non-volatile memory means and configured to provide a then-current record of ongoing accounting data; microprocessor means for writing accounting data into said non-volatile memory means in real time during each trip cycle of the postage meter and writing accounting data to said second volatile memory means only during power down cycles of the postage meter; A device for increasing the reliability of stored accounting data. (12) In an apparatus for increasing the reliability of stored accounting data reflecting the operations of an electronic postage meter, a first non-volatile memory means for storing accounting data reflecting the operations of the postage meter; microprocessor means for writing accounting data into said first non-volatile memory means in real time during each postage transaction; volatile memory means for storing accounting data reflecting postage meter operations; writing accounting data into said volatile memory means during each postage meter operation to provide a then-current record of accounting data about the transaction, and a second storing accounting data reflecting the postage meter operation;
non-volatile memory means for detecting a power-down condition and enabling said second non-volatile memory means for writing accounting data during a power-down cycle; said volatile memory means during a power-down cycle of the postage meter to provide two records of accounting data reflecting the operations of the postage meter written to said non-volatile memory means during two different cycles of operation. A device for increasing the reliability of stored accounting data, characterized in that it comprises: transferring existing accounting data to said second non-volatile memory means. (13) The device according to claim 12, wherein the first nonvolatile memory means is an EEROM. (14) The device according to claim 12, wherein the first non-volatile memory means is an EEROM, and the second non-volatile memory means is an MNOS memory.