JPS58144839U - Test probe card structure - Google Patents

Test probe card structure

Info

Publication number
JPS58144839U
JPS58144839U JP4126082U JP4126082U JPS58144839U JP S58144839 U JPS58144839 U JP S58144839U JP 4126082 U JP4126082 U JP 4126082U JP 4126082 U JP4126082 U JP 4126082U JP S58144839 U JPS58144839 U JP S58144839U
Authority
JP
Japan
Prior art keywords
probe card
test probe
card structure
integrated circuit
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4126082U
Other languages
Japanese (ja)
Inventor
藤田　年男
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP4126082U priority Critical patent/JPS58144839U/en
Publication of JPS58144839U publication Critical patent/JPS58144839U/en
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のテストプローブカードを示す図、第２図
は従来の接続構造を示す図、第３図は本考案の一実施例
であるテストプローブカードを示ス図、第４図は本考案
の一実施例である接続構成を示す図である。 図において、６はＩＣチップ（集積回路装置）、７は試
験テーブヲ、８は接地用の導体パ夛−ン、１１はテスト
プローブカード、１２はくり抜き孔、１３．１３’は接
続用端子、１４は接着樹脂、１５は信号用の導体パター
ンを示す。Fig. 1 shows a conventional test probe card, Fig. 2 shows a conventional connection structure, Fig. 3 shows a test probe card which is an embodiment of the present invention, and Fig. 4 shows the present invention. FIG. 2 is a diagram showing a connection configuration as an example of the invention. In the figure, 6 is an IC chip (integrated circuit device), 7 is a test table, 8 is a grounding conductor pattern, 11 is a test probe card, 12 is a hollow hole, 13.13' is a connection terminal, 14 15 indicates an adhesive resin, and 15 indicates a signal conductor pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に集積回路を形成してなる集積回路装置の機能試
験をする自動試験器において、該試験器のテストプロー
ブカードに環状の導体パターンが形成され、該導電パタ
ーンは接地されてなり、該導体パターシが前記集積回路
装置の接地端子に接続されてなることを特徴とするテス
トプローブカード構造。In an automatic tester for functionally testing an integrated circuit device having an integrated circuit formed on a substrate, a ring-shaped conductive pattern is formed on a test probe card of the tester, the conductive pattern is grounded, and the conductor is grounded. A test probe card structure characterized in that a pattern is connected to a ground terminal of the integrated circuit device.
JP4126082U 1982-03-24 1982-03-24 Test probe card structure Pending JPS58144839U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4126082U JPS58144839U (en) 1982-03-24 1982-03-24 Test probe card structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4126082U JPS58144839U (en) 1982-03-24 1982-03-24 Test probe card structure

Publications (1)

Publication Number Publication Date
JPS58144839U true JPS58144839U (en) 1983-09-29

Family

ID=30052445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4126082U Pending JPS58144839U (en) 1982-03-24 1982-03-24 Test probe card structure

Country Status (1)

Country Link
JP (1) JPS58144839U (en)

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