JPS58144758A - Waveform memory device - Google Patents

Waveform memory device

Info

Publication number
JPS58144758A
JPS58144758A JP2748782A JP2748782A JPS58144758A JP S58144758 A JPS58144758 A JP S58144758A JP 2748782 A JP2748782 A JP 2748782A JP 2748782 A JP2748782 A JP 2748782A JP S58144758 A JPS58144758 A JP S58144758A
Authority
JP
Japan
Prior art keywords
gain
offset
output
crt
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2748782A
Other languages
Japanese (ja)
Inventor
Toshihisa Suzuki
鈴木 敏久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP2748782A priority Critical patent/JPS58144758A/en
Publication of JPS58144758A publication Critical patent/JPS58144758A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00Arrangements for displaying electric variables or waveforms
    • G01R13/20Cathode-ray oscilloscopes
    • G01R13/22Circuits therefor
    • G01R13/225Circuits therefor particularly adapted for storage oscilloscopes

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)

Abstract

PURPOSE:To match outputs of bright lines with graduations on the surface of a CRT by correcting the gain and the offset with the calculation of errors therein from a deviation in the positions detecting them with a photoelectric conversion element when the bright lines are outputted on the CRT in varied voltages. CONSTITUTION:A fixed voltage is outputted on a CRT 1 as test signal through an output circuit 4 with a computation controlling circuit 3. At the same time, the position of the output is detected with a photoelectric conversion element 2 and the value is read into the computation controlling circuit. Then, a voltage different from the test signal is likewise outputted on the CRT 1 and the position of the output is detected with a photoelectric converter 2 to be read into the computation controlling circuit 3. Based on the difference between these two values, the circuit 3 calculates a deviation between the gain and the offset and outputs a value to correct the gain and offset. This automatically corrects the gain and the offset eliminating the deviation between graduations on the surface of the CRT 1 and the output positions.

Description

【発明の詳細な説明】 この発明は、ブラウン管を有する波形記憶装置において
使用される出力回路の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an output circuit used in a waveform storage device having a cathode ray tube.

入力アナログ信号をブラウン管上に表示するとともにデ
ィジタル化し、一時記憶した後、その信号をDA変換し
て再度ブラウン管上に出力する波形記憶装置において、
一般に出力回路のゲイン、オフセットは、温度変化等に
より変動する。このため、ブラウン管面上の目盛で読み
取る値と、出力値が一致しないという欠点があった。
In a waveform storage device that displays an input analog signal on a cathode ray tube, digitizes it, temporarily stores it, converts the signal from analog to analog, and outputs it again on the cathode ray tube.
Generally, the gain and offset of an output circuit fluctuate due to temperature changes and the like. For this reason, there was a drawback that the value read on the scale on the cathode ray tube surface did not match the output value.

本発明は、この欠点を除去するために自動補正回路を付
加したものである。
The present invention adds an automatic correction circuit to eliminate this drawback.

本発明は補正量を検出する手段として、ラインセンサ等
の光電変換素子をブラウン管に取付は用いたものである
The present invention uses a photoelectric conversion element such as a line sensor attached to a cathode ray tube as a means for detecting the amount of correction.

第1図、第2図及び第3図は本発明の実施例で第1図に
おいて、1はブラウン管、2はラインセンサ等の光電変
換素子でブラウン管の管面上に取付けられている。3は
演算制御回路で、テスト信号の発生、光電変換素子2の
出力により補正値を算出、出力回路のゲイン、オフセッ
トの制御ヲ行なう。4は出力回路で後に詳細に説明する
ようにDA変換器等により構成される。
1, 2, and 3 show embodiments of the present invention. In FIG. 1, 1 is a cathode ray tube, and 2 is a photoelectric conversion element such as a line sensor, which is mounted on the surface of the cathode ray tube. 3 is an arithmetic control circuit that generates a test signal, calculates a correction value based on the output of the photoelectric conversion element 2, and controls the gain and offset of the output circuit. Reference numeral 4 denotes an output circuit, which is composed of a DA converter and the like, as will be explained in detail later.

以下この動作について、演算制御回路3にマイクロプロ
セッサを使用した場合の例について説明する。
This operation will be described below with reference to an example in which a microprocessor is used in the arithmetic control circuit 3.

まず、演算制御回路3により、テスト信号として一定の
電圧を出力回路4を介しブラウン管1上に出力する。こ
の値がブラウン管の管面上のどの位置に出力されたかを
、光電変換素子1によって検出する。この光電変換素子
2の出力を演算制御回路3に読み込む。次に、前記テス
ト信号と異なる゛電圧を、出力回路4を介し、ブラウン
管上に出力させ、この位置を光電変換素子2により検出
し。
First, the arithmetic control circuit 3 outputs a constant voltage as a test signal onto the cathode ray tube 1 via the output circuit 4. The photoelectric conversion element 1 detects to which position on the surface of the cathode ray tube this value is output. The output of this photoelectric conversion element 2 is read into an arithmetic control circuit 3. Next, a voltage different from the test signal is outputted onto the cathode ray tube via the output circuit 4, and its position is detected by the photoelectric conversion element 2.

演算制御回路3に読み込む。Read into the arithmetic control circuit 3.

演算制御回路3では、この2つの値の差により。In the arithmetic control circuit 3, based on the difference between these two values.

オフセット及びゲインのずれを算出し、所定の値と一致
しているか判定する。異っている場合は。
The offset and gain deviations are calculated and it is determined whether they match predetermined values. If they are different.

ゲイン、オフセットを補正する値を出力する。次にゲイ
ン、オフセットの補正の一実施例について説明する。
Outputs values to correct gain and offset. Next, an example of gain and offset correction will be described.

第2図は、ゲイン、オフセットの補正出力をする出力回
路4の一実施例のプロ、り図であり、5は2図示しない
メモリに記憶したデータを入力とし・、これをアナログ
信号に変換する第1のDA変換器6は、第1−5!!4
′)D A変換器5の出力を増幅する増幅器、7は第1
ODA変換器5へaの基準電圧及びbの制御信号を与え
る第2のDA変換器。
Figure 2 is a schematic diagram of an embodiment of the output circuit 4 that outputs corrections for gain and offset, and 5 inputs data stored in a memory (not shown) and converts it into an analog signal. The first DA converter 6 is the 1-5th! ! 4
') An amplifier that amplifies the output of the DA converter 5, 7 is the first
A second DA converter that provides a reference voltage a and a control signal b to the ODA converter 5.

8は増幅器6へ補正用のオブセット電圧を与える第3の
DA変換器である。
8 is a third DA converter that provides an offset voltage for correction to the amplifier 6.

これら第2のDA変換器7及び第3ODA変換器8は演
算制御回路3に接続されている。
These second DA converter 7 and third ODA converter 8 are connected to the arithmetic control circuit 3.

ゲインを補正するには、−第2ODA変換器7に出力す
る値を変え、第1のDA変換器5のDA変換基準電圧を
補正する。
To correct the gain, - change the value output to the second ODA converter 7 and correct the DA conversion reference voltage of the first DA converter 5.

一方、オフセットを補正するには、第3のDA変換器8
に出力する値を変え、増幅器6のオフセットを補正する
On the other hand, in order to correct the offset, the third DA converter 8
The offset of the amplifier 6 is corrected by changing the output value.

また、第3図に示すように、ゲインの補正は直接増幅器
6で行っても良いことは言うまでもない。
Further, as shown in FIG. 3, it goes without saying that the gain correction may be performed directly by the amplifier 6.

以上説明したごとく2本発明によれば、波形記憶装置の
出力のゲイン、オフセットを自動m正fることかでき、
出力がブラウン管の管面上の目盛と一致する波形記憶装
置を得ることができる。
As explained above, according to the present invention, the gain and offset of the output of the waveform storage device can be automatically corrected.
A waveform storage device whose output matches the scale on the surface of a cathode ray tube can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明装置の一実施例のブロック図。 第2図及び第3図は本発明の一実施例のブロック図であ
る。 ■=ニブラウン、2:光電変換素子、3:演算制御回路
、4:出力回路、5:第1ODA変換器。 6:増幅器、7:第2ODA変換器、8:第3OD A
変換器。
FIG. 1 is a block diagram of an embodiment of the device of the present invention. 2 and 3 are block diagrams of one embodiment of the present invention. ■=Ni Brown, 2: Photoelectric conversion element, 3: Arithmetic control circuit, 4: Output circuit, 5: First ODA converter. 6: Amplifier, 7: Second ODA converter, 8: Third ODA
converter.

Claims (1)

【特許請求の範囲】[Claims] ブラウン管の管面上に取付られた輝線表示位置検出用光
電変換素子と、該光電変換素子に接続され、前記輝線表
示位置のずれによりゲイン、オフセットの誤差を算出す
る回路と、この誤差を補正する回路とを具備したことを
特徴とする波形記憶装置。
A photoelectric conversion element for detecting a bright line display position mounted on the surface of a cathode ray tube, a circuit connected to the photoelectric conversion element for calculating gain and offset errors based on deviations in the bright line display position, and a circuit for correcting this error. A waveform storage device comprising a circuit.
JP2748782A 1982-02-24 1982-02-24 Waveform memory device Pending JPS58144758A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2748782A JPS58144758A (en) 1982-02-24 1982-02-24 Waveform memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2748782A JPS58144758A (en) 1982-02-24 1982-02-24 Waveform memory device

Publications (1)

Publication Number Publication Date
JPS58144758A true JPS58144758A (en) 1983-08-29

Family

ID=12222480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2748782A Pending JPS58144758A (en) 1982-02-24 1982-02-24 Waveform memory device

Country Status (1)

Country Link
JP (1) JPS58144758A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62133363A (en) * 1985-12-02 1987-06-16 ソニー・テクトロニクス株式会社 Automatic calibration method and device for graduated cathode-ray tube

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62133363A (en) * 1985-12-02 1987-06-16 ソニー・テクトロニクス株式会社 Automatic calibration method and device for graduated cathode-ray tube

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