JPS58144253A - Converter for analog input - Google Patents

Abstract

PURPOSE:To improve the processing speed of a titled device without reducing the processing speed of a CPU, by using scan clock signals from a cyclic transmission device to perform analog-digital conversion cyclically. CONSTITUTION:Output signals of OR circuits OR of respective analog input units A, B, C and scan clock signals SA, SB, SC of the analog input units A, B, C are inputted to respective AND circuits AND and a trigger signal DO of an analog/digital converter ADC is generated by a signal obtained by forming the AND condition of both the output signal and scan clock signal. A cyclic transmission device SD2 scans said trigger signal and transmits the scanned signal successively and cyclically to the CPU through a cyclic transmission device SD1 and the CPU reads the digital data converted from prescribed analog data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention includes an analog-to-digital converter of a sequential comparison type in an input device, and converts an analog input signal into a digital signal by inputting a command signal from an arithmetic processing device based on a pre-stored quadrigram. The digital signal is converted into a signal and input to the arithmetic processing unit via a cyclic transmission device, and is suitable for use in a sequence controller capable of processing digital analog signals, a micro concillator, etc. The present invention relates to an analog input conversion device.

FIG. 1 shows an example of a conventional device, and is a 0Pt7
is an arithmetic processing unit (hereinafter simply referred to as CPU), y is an input device, 08D1 is a cyclic transmission device installed in the CPU @, BD2 is an input device Loading capacity is 8D1 and 8D2!
,90PU! : Enables signal transmission between the input device and the input device. B is an input device! The input device IN is generally equipped with a plurality of such analog input units. 8. 8. 8. 8.0 is another analog input unit whose configuration is the same as that of the analog input unit (B). Each analog input unit A, B, and O has an analog/digital converter DO and a latch circuit.

Equipped with an elaborate Y trigger pulse generation circuit TGt.

Since high-speed conversion is required as the analog-to-digital converter DO, a sequential comparison type is used.

The sequential comparison type analog-to-digital converter
The bits are sequentially set to ``1'' starting from the most significant bit F.

1lOj', and the point where the digital-to-analog conversion output and the input voltage are equal is searched for. Figure 2 is a diagram showing its principle, and converts the input voltage v1 to the analog signal input terminal A and N into a 4-bit digital signal f.
This is a reverse example of the case where the exchange is performed. First, in response to the timing signal T1, the 7 lip-flop circuits FF,
i Set.

Then, the digital output Do becomes @1000', so the voltage obtained by converting this digital signal into an analog signal by the digital-to-analog converter DAO is added to the comparator COM, and the comparator 00M is connected to this and the input voltage v1. Compare. With this, if the output is 11", the input voltage v1 is higher, and the converted value of the input voltage v1 is greater than "1000'@1xXX" (X means undefined. The same applies below). As you can see, the next timing signal T
.

At 7 flip-flop circuits Fl, the timing signal gate A) i D , ND,
.

MuND3. Close AND4. That is, comparator 00M
Since the output of is @1'', the output of the NOT circuit NO is Ilo'', and each of the above gates is closed. Next, the timing signal T comes, the flip-flop circuit SEAR is set, and the conversion output of "11QQ" is the input 1 voltage ViJ
: If t is high and t, the output of comparator 00M is llO”
So, this (1 each gate ANI), ,muMD,,muN
Since AND4 is opened, the 7-lip flop circuit Y1 is reset by the timing signal 〒4, and the converted value of the input voltage v1 is 110x''.In this way, μ
After that, the timing signal TIeT4*〒1. If T is given in sequence and each pin is checked, the analog-to-digital conversion will be completed and the digital output DOK will be the digital value of the input voltage v1 @timing signal T 1 e T! @...”
*The tie signal generation circuit TPG that outputs “a” sequentially outputs a series of tie signal Te3. 7. Stop.

Analog-to-digital converter D shown in FIG.

is the Australian analog signal input terminal "@*BleB1*B
In addition to the quantity address input to the standard quantity address input terminal MDD, the voltage input to the selected terminal can be selectively input to the analog signal input terminal MK. This is nothing special, it is commercially available, and the amount address prefixed by 0 is OPU.
The command information from 00PU, which is latched by a latch circuit via the cyclic transmission circuits BD, BD,', consists of a quantity address and a unit address. The force ζ cyclic transmission device flsp, not shown, is equipped with an internal unit decoder tube p, o.
The unit address from pry is the analog input unit selected by the user.

The latch circuit LK of B and O applies a latch signal LP that latches the address.The latch circuit LK temporarily stores the quantity address and sends its output to the analog to digital converter D.
The 0 trigger pulse generation circuit TP, which receives the address input terminal DD1 and the trigger pulse generation circuit τPK, is composed of an OR circuit OR and a monostable multivibrator 08. The latch circuit is cleared once before the quantity address is set. Therefore, by detecting the OR condition of each pit of the latch circuit ML, it can be seen that the latch circuit LK quantity address has been set. The monostable multivibrator 08 detects the rising edge of the output of the OR circuit and generates an analog signal.
A trigger signal is created to be applied to the trigger signal input terminal TR of the digital converter Do.

The OPU receives a predetermined signal from the input device N based on a program stored in the program storage section in advance.
All predetermined arithmetic processing is executed, and the results are sent to an output device (not shown) to control all of the controlled objects to a desired state. now,
Here, consider the case where an analog signal input to the analog signal input terminal B of analog input unit B is input.00PU outputs the information of unit address B and quantity address B as command information. do.

This command information is processed into the cyclic transmission device 8D1 and input into the cyclic transmission device BD2KIF.

Among these written nine pieces of information, the quantity address is generated by setting 1 to the unit address, and 1 to the friend latch signals I and F.
The analog signal input terminal B is temporarily stored in the latch circuit B of the analog input unit B. In addition, the analog signal input terminal B is connected to the analog signal input terminal M. Almost at the same time, the trigger pulse generation circuit TP detects that the quantity address has been temporarily stored in the latch circuit, and inputs the trigger pulse to the analog-to-digital converter. TPG is a series of Thailand-y Gubalus T1
5Tto"le..., when T@ is output, the conversion is completed and the tie-building pulse T11TltTl*...
The generation of ..., T, stops. And digital output D
o is a cyclic transmission circuit 8D2. 0 via BD1f diameter
0 or more that will be entered as PUK! 1117j on 5
Among the conventional ones, cyclic transmission device 8D2
cyclically and constantly, each digitally converted analog p
OPU the digital signal from input unit, B, 0.
However, in order to read the same analog signal again at a different timing, you must change the quantity address to another address and then set the predetermined quantity address again. If you do not do this, you will end up importing data that was converted in the past.This operation must be handled by the OPU program, but with conventional methods, the program is complicated and it is difficult to install. Click transmission device 8D1. A friend that has the disadvantages of 0PUO processing speed and slow response speed of the device due to the transmission cycle time of BD2.

The purpose of the present invention is to improve the response speed of the device to changes in analog input signals without impairing the processing speed It of 0Ptr. In order to improve the response speed to analog input signals, Always analog
It would be possible to perform digital conversion, but this is not possible with commonly used sequential comparison analog-to-digital converters. Therefore, the present invention focuses on the fact that the cycle time of the scan clock signal of a cyclic transmission device that transmits cyclic data is slow.The present invention is characterized by using this signal to perform cyclic The goal is to perform analog-to-digital conversion.

An embodiment of the present invention shown in FIG. 4 will be described below. The cyclic transmission device SD2 scans the digital outputs DOi from the analog input units (A, B, O) connected thereto, and sequentially and cyclically sends them out to the cyclic transmission device 8D1.For this reason, the cyclic transmission device 8D2 As shown in FIG. 3, a scan clock signal generation circuit for scanning the digital output DO from each analog input unit B and 0 is provided inside. Here, the scan clocks 8A, SB, and BC are for scanning analog input units A, B, and Ot, respectively. Therefore, we will create a trigger signal for the analog-to-digital converter DO using the scan clock signals S, 8B, and 80 and the signal caused by the quantity address signal being set in the latch circuit B.
That is, each analog input unit,=,O
The output signal of the OR circuit OR and the analog input circuits A and B.

Input the scan signal 8, 9B, and B○ of 0 to the AND circuit ND, and generate a signal from the analog-to-digital converter (DOCI) by the signal obtained by satisfying the AND condition of both signals. If this is set to Of5, the scan clock signal will be generated at regular intervals, so the trigger signal will also be output from the analog to digital converter at regular intervals.
L/C is input. Since the quantity address is latched by the latch circuit B, the analog input signal of the selected address is not digitally converted by the analog-to-digital converter MDC at regular intervals, and the converted digital data is latched by the latch circuit B. Click transmission-a via f8D2゜EID1i
transmitted to py. First, the OPU can convert predetermined analog data into digital data and read it.Therefore, once the CPU has set the child address, it will only read that data from now on.

In addition, all analog signals are cyclically converted to digital.
Since it can be transmitted to the PU, there is no need to create a special program in the CPU, and the response sequence of the device is improved.

In the above embodiments, each analog input (22)A,
The next scan signal assigned to B, 0 is assigned to unit 8, 8B.

BC is used to operate an analog-to-digital converter (AI)0, which inputs all the scan clock signals A, B, O, and outputs the respective scan clock signals B, sb, s. .

It may also be made to operate. This can be achieved by inputting the scan working clock signals 8m, EIB, and 0 into an OR circuit, creating a signal that combines all of them, and inputting the output of this OR circuit to an AND circuit. In addition, in the embodiment, on the condition that the address is set in the latch circuit 4, the analog-to-digital converter ADOQ is activated by the scan clock signals 8M, BB, and 80.
), but if the child address is set in the latch circuit 4 and there is no need to check whether it is b or not, the scan clock signals 8m, 8B, and 80 can be used directly to trigger the anarchy-to-digital converter. MDOI)! J Ga Suru 1
It's 41 good. Furthermore, since the embodiment is based on an example of an analog-to-digital converter DO that can accept multiple analog inputs, a quantity address is required to select it. If is singular, the following circuit is not needed due to the quantity address. Therefore, in this case, the analog-to-digital converter DOK receives only the scan clock signal as its trigger signal 1 in addition to the analog input. For example, it is possible to improve the response speed lt' of the device to changes in analog input signals without impairing the processing speed of the OPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional device, FIG. 2 is a block diagram showing an example of a sequential comparison analog-to-digital converter, and FIG. The time chart and FIG. 4 are block diagrams showing one embodiment of the present invention.0 ADO: Sequential comparative analog-to-digital conversion means, 8D
1,8D2: cyclic transmission means, OPU: arithmetic processing means f1 life addition signal

Claims (1)

[Claims] A sequential comparison type analog-to-digital conversion means for converting an analog input signal into a rainbow digital signal upon application of a trigger signal and outputting the same; and a digital output signal from the sequential comparison type analog-to-digital conversion means is cyclically converted to an arithmetic processing means. cyclic transmission means for transmitting data, wherein the scan clock signal of the cyclic transmission means is used as the trigger signal of the sequential comparison type analog-to-digital conversion means. .