JPS58143628A - Pulse width modulation circuit - Google Patents

Abstract

PURPOSE:To realize luminance control in multi-steps through simple circuit constitution, by fetching selectively the output of an n-bit counter by means of an n-bit digital signal showing the luminance level. CONSTITUTION:In case three bit outputs L2, L1 and L0 of a memory register 3 are set at 0, 0 and 0, respectively, the outputs of AND circuits 6, 7 and 8 are all set at 0. Thus a pulse signal which has the smallest width and is set at H level just for a period during which a terminal -S is kept at L level is obtained at an output terminal P of an RS flip-flop. Then the outputs L2, L1 and L0 are set at 0, 0 and 1, respectively. In this case, the output -R of an OR circuit 9 is set at Q0 and the state of the terminal P becomes as shown by tau1. IN the same way, the -R is set at Q2 in case the outputs L2, L1 and L0 are set at 0, 1 and 1 respectively and tau3 is obtained at the terminal P. Thereafter, the avove-mentioned outputs L2, L1 and L0 are varied in the same way to obtain luminance evels in 8 steps (tau0, tau1-tau7).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation circuit in a multi-mode display device that performs pulse width variation gMiLA brightness control on a digital signal and displays an image gI.

In general, in matrix display devices, brightness If control is often performed using digital signals. The 11th ψ is a block diagram showing the configuration of a general matrix display device. In FIG. 1, reference numeral 1 denotes a matrix panel consisting of three X electrodes X, X, . . . xN and M Y electrodes Y, Y, . Place a gas discharge element, electroluminescent element, light emitting diode, liquid crystal, etc. at the intersection of the X electrodes and apply a signal voltage to the X electrodes.
Therefore, the luminance of light emission or the transmittance of light is changed to display an image. 2 is an X electrode scanning circuit, 3 is a memory register,
4 is an X electrode drive circuit. The operation will be explained clearly using FIG. 1 below. The matrix panels 1 are selected one by one by the X1r pole scanning circuit 2, and an X electrode drive signal is applied.

On the other hand, to the Y [pole, an X electrode drive signal corresponding to the luminance level of the Yfi pole drive circuit 4 and the person's name X electrode Y, Y, Y, . . . YM is applied. Therefore, the input signal to the X electrode drive circuit 4 is given from the memory register 3, and its contents are expressed as 3-bit digital signals Ly and Ls-Lo with 8 brightness levels. Table 1 shows the relationship between the signals.

Table 1 Digital signals L, L, are updated every time the X electrode is switched and are held in the memory register ST/C until the next X electrode is selected.

The brightness control of the X electrode in such a matrix display device is generally done in order to downsize the circuit and stabilize its operation. 4
This is done by converting a digital signal representing two levels into a pulse width signal (hereinafter referred to as pulse width modulation). The pulse width modulation circuit is an important component of the X electrode drive circuit shown in Figure $1.

FIG. 2 is a circuit diagram showing a pulse width modulation circuit according to the prior art.

FIG. 3 is a timing chart explaining the operation of the WJ2 diagram.

In Fig. 2, N, -%-N, is an inverter, 1 to 5 person circuit, G, ~G, s, 2 person circuit G1
6 is an 8-person Chaor circuit.

The output P of this pulse width modulation circuit is expressed by the following logical formula (1) where the input signal τ. ~τ is a pulse width signal generated in synchronization with a strobe signal (hereinafter referred to as 8TB) that sets the X electrode selection period tx, as shown in FIG.
O1τ1. The subscripts τ,, r, ... τ correspond to the brightness levels 0 to 7 in Table 1. (TO and τ.

(not shown) τ0 is always a signal of ζ'', and τd is always a signal of ``. τ words to τ6 are generated by a monostable multi or shift register. Input signal L.

Lo is the output of the memory register shown in FIG. 1, and is a 3-bit digital signal representing the brightness level. L
The contents of t, Lt, and Lo are updated in synchronization with the STB signal as shown in the third column, and the contents are held for the period of tx. As is clear from equation (1), the operation of the circuit in Figure 2 is 3
Bit digital signal L! , L,, depending on the content of L, τ. ~τ, corresponding to the brightness level of the X electrode from G16 1. This outputs the pulse width.

M) In the IJ display device, each X electrode Y.

Since a pulse width modulation circuit is required for each of Y, Y, . However, the circuit in Figure 2 requires the same number of selection gates and pulse width signals as the number of brightness levels, so if the number of brightness levels is increased, that is, the number of bits of the digital signal representing the brightness level is increased, the circuit becomes extremely complex. Then, IC
There was a problem in that the chip size was extremely large.

Furthermore, as a conventional example for the purpose of simplifying the brightness modulation circuit, the system shown in FIG. 4 is already known. The waveform diagram in Figure 4 is from Figure 4 of Japanese Patent Publication No. 50-26249.
This is shown in FIG. The wJ4 diagram will be briefly explained below.

In the figure, T,, T,, T, are weighted so that the pulse width ratio is 1:2:4, with the time obtained by dividing the two periods tx during which one X electrode is selected into 7 equal parts, 17, as 1. This is the signal attached. The brightness modulation of this method is T.

The pulses of T, , T, are selectively taken out by digital signals representing the brightness level, L, , Lo,
τ in Figure 4. This is done by obtaining a brightness modulation pulse of ~τ, 08 steps. At first glance, the method described above appears to be able to perform pulse width modulation with a relatively simple circuit configuration. However, as can be seen from the waveform τ in FIG. 4, there is not one continuous pulse, but a break occurs in the middle. In other words, the number of inversions increases.

In actual hardware, the inverted part of the waveform is @
The presence of this waveform 1 accent deteriorates the fidelity of brightness reproduction in applications such as liquid crystal displays.

For simplicity, Fig. 4 has been explained using a 3-bit example, but in reality, it is desirable to use approximately 6 bits or more for image reproduction, and in this case, the number of waveform inversions will further increase. and the fidelity deteriorates. This deterioration was a serious drawback of the above-mentioned prior art.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse width modulation circuit that eliminates the drawbacks of the prior art described above and enables multi-step brightness control with a simple circuit configuration.

In the present invention, up to 20 types of pulse width signals can be obtained by using n gate circuits and one OR circuit that selectively take out the output of an R8 flip-flop and an n-bit counter using an n-bit digital signal representing the brightness level. .

Embodiments of the present invention will be described below with reference to the drawings.

@Figure 5 is a circuit diagram showing the first embodiment of the present invention. FIG. 6 is a timing chart illustrating the operation of the circuit shown in FIG.

The pulse width modulation circuit shown in FIG. 5 consists of a 5-bit binary counter 5. 2-person AND circuit 6 with 5.5 memory registers
, 7, 8. 2-person canando circuit configuring a 3-person chaor circuit 9° R8 flip-flop 10. -11. Here, the 3-bit binary counter 5 is common to all the X electrode drive circuits. 5 2 person road 6, 7.8
, 5 person Chaoa circuit? , R8 The NAND circuit 10.11 constituting the flip-flop has each X electrode Y,, Y,...
One circuit is required for each YM. The operation of the circuit shown in FIG. 5 will be explained below using the timing chart shown in FIG. The binary counter 5 is reset by the STB signal supplied to the STB terminal and counts six clock pulses CP during the tx period when one X electrode is selected. Q,, Q.

0 is the negative output of the 3-bit binary counter 5.

The output of memory resistance 45 is 8T.
Each X electrode Y1. The contents are updated according to the brightness levels of Y, - YM, and are held until the next X[pole is selected. The timing is shown in FIG. 6, IL+, and Lo. The operation of 10.11 is that when the STB signal is applied to the input terminal 8, the output terminal P becomes @H due to the 1L'' level of STB.
” level.

Next, when an @L" level signal is applied to the R terminal, the output terminal P becomes "L" level.

Next, the overall operation will be explained. When the memory register 303 bit output (LoL+1Lo) is (ooo), the output of the AND circuit 6=7+8 becomes 0, so the OR circuit 9
The output is also OK. Therefore, when the contents of LuLtLe are updated as shown in the timing chart R in FIG. 6 when (L, L%Le) is (000), the R terminal is
Ic@L” level.

Become. Therefore, the output terminal P of the R8 flip 70 tube is
As shown in the timing chart in Figure 6, the 100 terminals are “
The narrowest pulse width signal is obtained, which is at the "H" level only during the L" level period.

Next, the output of memory register 6 (Lt-Lt-Lo) is (
001), L, , L, , Lo are AND circuits 8
, 7.6, an AND operation is performed with Q, , Q, , Q, and only q is output to the output R of the OR circuit 9. R is (
As shown when Lt, Lt, Lo) is (001), q
The waveform is the same as that of Therefore, as shown in the timing chart τ1 in FIG. 6, the output terminal P of the R8 flip-flop becomes the ")J" level due to the S signal, and at the 01st rising edge of the clock pulse CP, the ""L"L" level pulse is output. A width signal is obtained. Similarly, when the output (Ly, play, Lo) of the memory register 3 is (011), tin, Q, passes through the AND circuit 6.7, an OR operation is performed in the OR circuit 9, and R is the clock pulse. The waveform shown in the timing chart of FIG. 6, which starts from the third rising edge and reaches the "L" level (when L*-L+-L(1) is (011)), becomes the "L" level. Therefore, the output terminal P of the R8 flip-flop outputs a pulse width signal shown in the timing chart τ in FIG.

Similarly, memory register LI1. L,, L
.

By selectively extracting only the output of the binary counter corresponding to the @H'' level bit of the 3-bit digital data of It is possible to obtain the reset signal of R8 flip-flop of Seken, and τQ
l τ2. τ.

...Pulse output P that provides 8 levels of brightness levels
is obtained. τQl τII τ鵞...τ! 8 brightness levels and memory register L0. Table 1 shows the correspondence with the contents of L,,L,.

Next, a $2 embodiment of the present invention will be described with reference to FIGS. 7 and 8.

FIG. 7 is a logic circuit diagram showing the @2 embodiment of the present invention;
The figure is a timing chart explaining FIG.

The OR circuit 9 in FIG. 5 is replaced by a 4-person COR circuit 12 in FIG. 7, and the OR circuit 9 of FIG. However, this is different from the first embodiment. The operation of the circuit shown in FIG. 7 will be explained below using the timing chart shown in FIG.

The output of the binary counter 5 is Q, , Q, (4 is the output of the memory register 3 because two or more bits change at the same time in the parts A, B, and C as shown by the broken line in Fig. 8). If two or more of the bits Q, L, and Lo are at the 1H'' level, an OR operation is performed on two or more bits of Q, Q, Q, and as a result, the R signal has a width due to the phase difference. narrow pulses (hereinafter referred to as whiskers) may occur.

The second embodiment is a circuit that prevents malfunctions caused by this whisker. Now considering the case where the output (LlLt, M) of the memory register 3 is (Ojl), the outputs Q, , , Q of the binary counter 5 each pass through the AND circuit 6.7 and are processed in the OR circuit 12. A logical sum operation is performed. In part A shown in the timing chart of Fig. 8, q changes from @L''' level to @H'' level, and Q changes from @HII level to 1LI.
l level, so if the change in q is slower than the change in Ql, a whisker will occur in part A, and the pulse width will become @L'' level by the pulse width of the phase difference.When this whisker is input to R of the R87 lip-flop, 8TB The output P, which was set to @H'' level, reverses to the "L" level before the predetermined pulse width and remains 1H' until the next 8TB signal is input.
In order to prevent such malfunction, in the circuit of FIG. 7, the clock pulse C of the binary counter 5
P, and the output of the memory register, L,.

Binary counter output Q1. is selectively outputted as a trap depending on the contents of Lo. Ql, I'm trying to do a logical sum with Qi. Therefore, the whisker generated by the logical sum of QA and Q occurs while the clock pulse CP is at the s Hn level, so no whisker occurs in the R output. By doing this, the output P of the R8 flip-flop becomes the clock pulse CP.
At the third fall of t, the pulse width signal becomes ``L'' level as shown by τ in the timing chart of FIG.

Similarly, the memory registers L,, L,, L, 0
The timing shown in Fig. 48 is obtained by selectively extracting the output of the binary counter corresponding to the @HI+ level bit of the 3-bit digital data and performing an OR operation with those signals and the clock pulse CP of the binary counter. As shown in the chart, the output Q of the binary counter is
It is possible to obtain an 8-hinoki reset pulse that does not generate whiskers even if there is a phase difference in the portion where two or more Q, Q, change simultaneously, and τ0. A pulse width signal of l or SSa is obtained in synchronization with the falling edge of the clock pulse CP of τ, .

In the above embodiments, the brightness level has been explained as a 5-bit digital signal, but it goes without saying that the present invention is generally applicable to n-bits.

As is clear from the above description, according to the pulse width modulation circuit of the present invention, the output of the n-bit binary counter is selectively extracted using the n-bit digital signal indicating the brightness level, and the logical sum signal is used to extract the output of the n-bit binary counter. , in order to reset the R8 flip-flop set by the reset pulse of the binary counter, the circuit configuration consists of only n selection gates, one OR circuit, and 70 R8 flip-flops,
Even when the brightness level is increased, there is no significant increase in the number of circuits, and the matrix display neck can be made smaller.

Next, an embodiment of a dynamic bistable circuit using a MOS transistor that can be used in the present invention will be described. @
Figure 9 shows a circuit diagram of a bistable circuit using MOS transistors.

The circuit of FIG. 9 has power terminal 15. Set input terminal 14, reset input terminal 15. N-channel MOS transistor 16. P channel MO8) Run raster 1f, output terminal 18. It is composed of a capacitor 19. The operation will be explained below.

``L'' level signal once to set input terminal 14 4
When input, P channel N08) transistor 17 turns on, charges capacitor 19, and output terminal 1B becomes ``''
A signal of 1H" level arrives at the reset input terminal 15, and the N-channel MOS) transistor 1
``H'' due to the charge of capacitor 19 until 6 turns on.
Hold the level.

Also, once the @H'° level signal arrives at the reset input terminal 15 and the output terminal 18 becomes the 19"L" level, the @L" level signal is input to the set input terminal 14 until the @L" level signal is input.
″Hold the level.

Therefore, using the bistable circuit described above in the R8 flip-flop section constituted by the NAND circuit 10.11 in the circuit of the embodiment shown in Fig. 5 and @Fig. This is possible by making it into a circuit.

According to the pulse width modulation circuit of the present invention, it is possible to provide a pulse width modulation circuit that outputs pulse widths corresponding to multi-step luminance levels represented by a digital luminance signal with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a block J# showing the configuration of a general Ma) FIG. 4 is a waveform diagram showing a brightness modulation method according to the prior art. Fig. 5 is a logic circuit diagram showing the first embodiment of the present invention, and Fig. 6 is a timing chart explaining the 5M. FIG. 7 is a logic circuit diagram showing the $2 embodiment of the present invention, and FIG. 8 is a timing chart explaining the @7 embodiment. @9 Figure is a circuit diagram of a MOS) Langimeta bistable circuit used in the present invention. No. A, 8/71 So1. Kusu Baoru 2° /re register 29 4・Y
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Claims (1)

[Claims] In a pulse width modulation circuit that converts a digital signal (n: an integer) into a pulse width signal, a bistable circuit that sets the output to one state by a trigger pulse, an n-bit binary counter, and the n-bit 2 n gate circuits that selectively take out the n outputs of the decimal counter according to the state of each bit of the n-bit digital signal; the outputs of the n gate circuits are logically operated and the n-bit digital signal is pulsed; A pulse width modulation circuit comprising a logic circuit that converts a signal including width information, and inverting the bistable circuit to the other state by an output of the logic circuit.