JPS58143610A - Amplifier - Google Patents

Abstract

PURPOSE:To prevent the generation of offset voltage due to each MOST (MOS transistor), by having coincident working characteristics of feedback resistance between positive and negative cycles of an input signal. CONSTITUTION:The characteristics of p channel MOST8 are set coincident with thoes of an n channel MOST7 between positive and negative cycles of an input signal. As a result, the working characteristics of feedback resistance are coincident between the positive and negative cycles of the input signal. This coincidence is attained by obtaining the same mutual conductance between p and n channel MOSTs. In case an AC input vi is added to the DC bias voltage Vi at an input terminal 5 by capacitive coupling, an AC -Avi is added to a DC component Vi for the output voltage at an output terminal 16 as long as an AC amplification factor -A of an inverter 4 is linearly amplified. Therefore a current flows toward the terminal 6 from the terminal 5 via each MOST in terms of the positive half cycle of an AC input. Thus the terminals 5 and 6 function as sources.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier that can always set an appropriate input bias for input signals ranging from small signals to large signals.

FIG. 1 shows a frequency divider circuit and an amplifier for generating a clock to the frequency divider circuit.

Conventionally, in a 0M08 circuit, etc., in order to apply an input bias to the input of a small signal applied via a capacitor Ci, one side is connected between the input and output terminals 2 and 3 of a CMOS inverter 1 as shown in FIG. Polar MOS) transistor (hereinafter referred to as M2S) Connect the source and drain of Rf,
Its gate was connected to one power supply, and this MO8TRf was used as an active feedback resistor.

In the example of FIG. 1, MO8T used as the feedback resistor Rf has sufficiently small mutual conductance. Below, we will discuss the problems when using the circuit shown in FIG. 1 at high frequencies.

When the input signal Z7i is large, the operation of MO8TRf used as the feedback resistor is such that the gate voltage to the source of MO8TRf' is different in the positive half cycle and the negative half cycle, and the feedback resistor Rf exhibits nonlinearity. , produces an offset in the DC bias v1 of the input terminal 2.

When this input offset voltage occurs, inverter 1
How the waveform at the output end 3 changes is shown in the case where there is no offset in FIG. 2a and in the case where there is an offset in FIG. 2a. As is clear from the figure, if an offset occurs in the input, due to the characteristics of inverter 1,
Since each negative half cycle is determined based on Vi,
Naturally, the duty for the operating output of 0" and "1" in each pressure/negative cycle will change. In particular, input signal 1
) As the frequency of s becomes higher, the amplification degree of the amplifier decreases, and therefore the input signal level must be increased.

As described above, in the conventional example, there is a problem in that the higher the frequency of the input signal, the more the offset of the input bias occurs, making it impossible to operate the input signal υS at the optimum operating point of the inverter.

The present invention aims to provide an amplifier in which no offset occurs even if the input signal has a high frequency. That is,
The present invention uses p-channel and n-channel resistors as feedback resistors.
The channel type MO8T is connected in a complementary manner, and the input signal positive,
This prevents offset voltage from occurring by matching the characteristics of the p-channel MO8T corresponding to each negative cycle with the characteristics of the n-channel MO8T corresponding to each negative and positive cycle of the input signal. It is.

Hereinafter, the configuration of the present invention will be explained using the drawings.

FIG. 4 shows an embodiment of the present invention. An n-channel type MO8T7 and a p-channel type MO8T8 are connected complementary between the input and output 6 and 6 of the inverter circuit 4, and the gates of each are connected to G.
Connected to ND and VDD. p of inverter circuit 4
, n Both channel transistors are enhancement mode transistors, and the mutual conductance is (GWp+ 'u
n ) are approximately equal, and the threshold voltage (vTpl
It is assumed that the absolute values l vrp l and l vTnI of vTn) are approximately equal.

When there is no input signal, the voltage at the input terminal 6 and the output terminal 6 is returned to the input via the MO8T7゜8, which serves as a feedback resistor, and the voltage at the input terminal 5 side is
When the input impedance of T is approximately, the drain-source voltage of both MO8s 7 and 8 is O, so no current flows.

Next, it is assumed that an AC human power Z7i is applied to the input terminal 5 in addition to the DC bias voltage vi through capacitor coupling. Assuming that the AC amplification factor of the inverter is -m and that the amplification is linear, the output voltage at the output terminal 6 is 1m v for the DC component Vi.
The exchange of i will be added. Therefore, if we consider a positive cycle of AC input (Z/i>O), current will flow from terminal 6 to terminal e through each MO8T, and therefore, p-channel MO8T8 has terminal 6 as the source and n In channel MO8T7, terminal 6 operates as a source. Also, the negative cycle of AC input (vl<0)
Then, p-channel MO8T8 has terminal 6 as the source,
In the n-channel MO8T7, the terminal 6 operates as a source. This means that when looking at the input terminal 6 and the output terminal 6 as a reference, for the p-channel MO8T8, the input signal is positive,
The negative cycle operation corresponds to the negative and positive cycles of the input signal of the n-channel MO8T7. Therefore, the characteristics of the p-channel MO8T8 in the input signal positive cycle, the characteristics of the n-channel MO5T7 in the input signal quality cycle, and the p-channel MO5 in the input signal quality cycle
Characteristics of T8 and n-channel MO of input signal positive cycle
By matching the characteristics of the 5T7, the operating characteristics of the feed bank resistor will match during both positive and negative cycles of the input signal. This can be achieved by operating the MO8T in such a way that the mutual conductances of both the p-channel MO8T and the 1-channel MO8T are the same. In this way, if the operating characteristics of the feedback resistor are matched during the positive and negative cycles of the input signal, the p-channel and n-channel M
Since the operation of the O8Ts can be matched for two cycles, no offset voltage occurs due to non-linearity of the respective MO8Ts.

Therefore, if the value of the feedback resistor is determined so that the mutual conductance of both channels is equal to p+, there is almost no offset voltage of the input bias voltage caused by the magnitude of the input signal, and therefore, as described in the conventional example, No such inconvenience will occur.

In the above embodiment, p of the inverter.

Although the example has been explained in which the mutual conductance and threshold voltage of the transistors of both n channels are approximately equal, even if this is not the case, in the present invention, the input voltage can be generally adjusted by making the mutual conductance of the feedback resistor equal at its operating point. It is possible to prevent offset voltage from occurring due to the magnitude of the signal amplitude.

As described above, according to the present invention, an input signal does not cause an offset voltage in the input bias, and
The input sensitivity is not deteriorated, and the operating point of the inverter is optimized, so that high-frequency operation can be performed to its maximum limit.

In this embodiment, a circuit with a feedback resistance of 0M08 is used, but the same operation can be performed with a circuit using a J-FET, an inverter circuit, an n-channel E/D circuit, a J-FICT, etc. It is clear that this can be done.

Further, in this embodiment, an example has been described in which negative feedback is provided to the feedback resistor from the first stage of the amplifier, but it is clear that the present invention is also applicable to a case where negative feedback is provided from the general odd-numbered stages.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an amplifier and a frequency dividing circuit in a conventional example.
Figure 2 is a schematic diagram of operating waveforms with and without offset voltage.
FIG. 3 is a circuit diagram of an amplifier according to an embodiment of the present invention. 4... Inverter circuit, 6... Input end, 6... Output end, 7, 8... n for feedback resistance. p channel MO80

Claims (3)

[Claims] (1) An amplifier circuit that inverts an input signal, and a first and second amplifier circuit with different polarities connected between the input and output terminals of the amplifier circuit.
and a field effect transistor of the first. Source of the second field effect transistor. An amplifier characterized in that drains are connected in a complementary manner, a gate of the first field effect transistor is connected to a first power source, and a gate of the second field effect transistor is connected to a second power source. (2) First. 2. An amplifier as claimed in claim 1, characterized in that the transconductances of the second field effect transistors are approximately equal. (3) The amplifier according to claim 1 or 2, wherein the amplifier circuit is constituted by a C-MOS inverter.