JPS58142541A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58142541A
JPS58142541A JP2624582A JP2624582A JPS58142541A JP S58142541 A JPS58142541 A JP S58142541A JP 2624582 A JP2624582 A JP 2624582A JP 2624582 A JP2624582 A JP 2624582A JP S58142541 A JPS58142541 A JP S58142541A
Authority
JP
Japan
Prior art keywords
film
etching
oxide film
type semiconductor
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2624582A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sakai
坂井 弘之
Toyoki Takemoto
竹本 豊樹
Kenji Kawakita
川北 憲司
Tsutomu Fujita
勉 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2624582A priority Critical patent/JPS58142541A/en
Publication of JPS58142541A publication Critical patent/JPS58142541A/en
Priority to US06/660,255 priority patent/US4563227A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

PURPOSE:To obtain a fine MOS device by eliminating the generation of bird heads at the time of selective oxidation by a method wherein an Si3N4 film is stably left only on the side surface of the aperture of an Si substrate. CONSTITUTION:An SiO2 film 22 and an Si3N4 film 23 are superposed on the P type Si substrate 21, then the films 23 and 22 are opened by applying a resist mask 24, and when the substrate 21 is slightly etching-removed, the side surface is also etching-removed. Next, an aperture 21c is vertically provided by reactive ion etching, then B ions are implanted, and accordingly a channel stopper 25 is formed. An Si3N4 film 27' is provided over the entire surface by removing the mask and covering the aperture part with a thermal oxide film 26. An Si3N4 film 27' is left on the side surface of the aperture in self-alignment by reactive ion etching. Next, an SiO2 28 is formed by selective oxidation. Since bird heads are hardly generated, and a very deep field oxide film and a channel stopper are formed by this method, a fine MOSFET which has very high density and high accuracy and does not have the effect of narrow channel can be obtained.

Description

【発明の詳細な説明】 本発明はMO8半導体装置の高密度化、高精度化ならび
にしきい値電圧vthの安定化を図った半導体装置の製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a MO8 semiconductor device that achieves higher density, higher precision, and stabilized threshold voltage vth.

近年、MO8半導体装置はます1す高密度化の要求が高
まり、リソグラフィ技術の進歩と共に急速な進歩を遂げ
ている。しかしながら、高密度になるとともに従来のデ
バイスでは起こらなかった新しい現象として、ショート
・チャネル効果、狭チャネル効果等が大きな問題となっ
てきている0シヨートチヤネル効果はゲート長が短くな
るにつれてvthが小さくなり、狭チャネル効果はゲー
ト幅が短くなるにつれて、vthが大きくなるという現
象である0ショート−チャネル効果に関しては、よく研
究がされ、基板の不純物濃度を高くすることが最も良い
方法であることがわかり、いろいろな工夫により、ショ
ート・チャネル効果を防ぐ対策がされている。しかしな
がら、狭チャネル効果については最近ようやく解析が始
まシ、まだ充分な対策がされていないのが現状である。
In recent years, demands for higher density MO8 semiconductor devices have been increasing, and rapid progress has been made with advances in lithography technology. However, as density increases, new phenomena that have not occurred in conventional devices, such as short channel effect and narrow channel effect, have become major problems.As the gate length becomes shorter, vth becomes smaller. Regarding the narrow channel effect, which is a phenomenon in which vth increases as the gate width becomes shorter, extensive research has been conducted, and it has been found that the best method is to increase the impurity concentration of the substrate. Various measures have been taken to prevent the short channel effect. However, analysis of the narrow channel effect has only recently begun, and the current situation is that sufficient countermeasures have not yet been taken.

従来のMO8半導体装置の構造を第1図に示す。The structure of a conventional MO8 semiconductor device is shown in FIG.

1はたとえばp型半導体基板、2はチャネル・ストッパ
ーであり、フィールド酸化膜形成時に生じる反転層を打
ち消す効果を有している。3はフィールド酸化膜であり
、4はゲート酸化膜である。
Reference numeral 1 designates, for example, a p-type semiconductor substrate, and 2 designates a channel stopper, which has the effect of canceling out an inversion layer generated when forming a field oxide film. 3 is a field oxide film, and 4 is a gate oxide film.

5はpozyst  ゲート、6はソース及び6′はド
レインである。7は配線用のCV D (Chemic
atVapor Deposition  )法により
形成された酸化膜であり、8はAt配線である。
5 is a pozyst gate, 6 is a source, and 6' is a drain. 7 is CV D (Chemical) for wiring.
This is an oxide film formed by the at Vapor Deposition method, and 8 is an At wiring.

狭チャネル効果に関しては、チャネル・ストッパーとし
て形成したp型拡散領域2が熱処理によって横方向にも
拡散され、フィールド酸化膜3を通り越して、チャネル
部にも広がってくるため、チャネル部、4!にフィール
ド酸化膜との境界付近で不純物濃度が高くなっているこ
とが原付と考えられる。チャネル幅が広いときはフィー
ルド酸化膜との境界付近でチャネル部の不純物濃度が高
くなってもチャネル中央付近にはほとんど影響しないが
、チャネル幅が短くなってくるとチャネル・ストッパー
のp型拡赦領域の横方向への入り込みが、チャネル部の
端部だけでなく、チャネル部全体の不純物濃度を高くす
るため、狭チャネル効果を起こすと思われる。狭チャネ
ル効果を防ぐためには、チャネル・ストッパーが横方向
に拡散されても、チャネル部の不純物濃度に影響しない
程度に距離を離せばよい。しかしながら、通常のMOS
プロセスではチャネル・ストノハートフィールド酸化膜
は一枚のマスクで自己整合的に形成するので、チャネル
・ストッパーとフィールド酸化膜の距離を離すには新た
に一回マスク合せをする必要があり、工程が増えること
になる。また、フィールド酸化膜を深く形成して、チャ
ネル・ストッパーとチャネル部を離そうとすれば、選択
酸化の際に生じる横方向の酸化、いわゆるbird& 
beakが大きくなり、やはり高密度化の妨げとなる。
Regarding the narrow channel effect, the p-type diffusion region 2 formed as a channel stopper is also diffused in the lateral direction by heat treatment, passes through the field oxide film 3, and spreads into the channel region, so that the channel region 4! It is thought that the impurity concentration is high near the boundary with the field oxide film. When the channel width is wide, even if the impurity concentration in the channel part increases near the boundary with the field oxide film, it has almost no effect on the center of the channel, but as the channel width becomes shorter, the p-type expansion of the channel stopper increases. It is thought that the lateral intrusion of the region increases the impurity concentration not only at the end of the channel section but also at the entire channel section, thereby causing a narrow channel effect. In order to prevent the narrow channel effect, even if the channel stopper is diffused in the lateral direction, the distance between the channel stopper and the channel stopper may be set to such an extent that it does not affect the impurity concentration in the channel portion. However, normal MOS
In the process, the channel stopper and heart field oxide film are formed in a self-aligned manner using a single mask, so in order to increase the distance between the channel stopper and the field oxide film, it is necessary to align the mask once again, which reduces the process time. It will increase. Furthermore, if the field oxide film is formed deeply to separate the channel stopper and the channel part, lateral oxidation that occurs during selective oxidation, so-called bird&
The peak becomes large, which also hinders high density.

本発明はこのような問題の検討に鑑み、従来のMO8半
導体装置では防ぎきれない狭チャンネル効果を、素子を
高密度・高精度にするにもかかわ6 ど−二 らず、押さえることができvthの変化の小さい半導体
装置の製造方法を提供するものである。
In consideration of such problems, the present invention has been developed to suppress the narrow channel effect, which cannot be avoided in conventional MO8 semiconductor devices, even though the device is made to have high density and high precision. The present invention provides a method for manufacturing a semiconductor device with a small change in .

第2図に我々が先に提案した絶縁分離膜の形成方法を示
す。同図Aにおいて、11はたとえばp型半導体基板、
12は下地酸化膜、13は酸素を通過しない窒化ケイ素
膜、14は酸化膜でp型半導体基板11をエツチングし
て形成した開口部11′の側面及び底面に形成されてい
る。16は13と同じ酸素を通過しない窒化ケイ素膜で
あり、窒化ケイ素膜13の端部からp型半導体基板を開
口した部分の側面にのみ形成されており、底面には形成
されていない。この構造はp型半導体基板11をエツチ
ングする時、第1ステツプとしてケミカルエツチングあ
るいは等方的なドライエツチングによってサイドエツチ
ングをおこしながら開口しく図中16で示している部分
)、第2ステツプとして異方性の強いドライエツチング
によって、マスクパターンに忠実にしかも垂直に所定量
開口した後、酸化膜14及び窒化ケイ素膜16を形成す
ることにある。酸化膜14はp型半導体基板116 ベ
ー、゛ を開口して開口部11′を形成した後、全面熱酸化する
ことによって、窒化ケイ素膜13上には酸化膜は形成さ
れず、p型半導体基板11を開口した部分にのみ形成す
ることができる。
FIG. 2 shows the method for forming an insulating separation film that we previously proposed. In the figure A, 11 is, for example, a p-type semiconductor substrate,
12 is a base oxide film, 13 is a silicon nitride film through which oxygen does not pass, and 14 is an oxide film, which are formed on the side and bottom surfaces of an opening 11' formed by etching the p-type semiconductor substrate 11. 16 is a silicon nitride film that does not allow oxygen to pass through, like 13, and is formed only on the side surfaces of the opening of the p-type semiconductor substrate from the end of the silicon nitride film 13, and is not formed on the bottom surface. When etching the p-type semiconductor substrate 11, the first step is chemical etching or isotropic dry etching to create an opening (the area indicated by 16 in the figure), and the second step is anisotropic etching. The purpose is to form an oxide film 14 and a silicon nitride film 16 after forming a predetermined amount of openings perpendicularly and faithfully to the mask pattern by a strong dry etching process. The oxide film 14 is formed by opening the p-type semiconductor substrate 116 to form the opening 11' and then thermally oxidizing the entire surface, so that no oxide film is formed on the silicon nitride film 13 and the p-type semiconductor substrate 11 can be formed only in the open portion.

第2図では熱酸化によってp型半導体基板を開口した部
分にのみ酸化膜14を形成しているが、CV D (C
hemicatVapor Deposition )
法により、窒化ケイ素膜13上にも酸化膜を形成しても
別に構わない。窒化ケイ素膜16はCVD法により全面
形成した後、異方性の強いドライエツチングによって、
全面エツチングすれば、p型半導体基板11を開口した
底面部分及び蟹化ケイ素膜13上に形成された窒化ケイ
素膜15のみがエツチングされ、開口された部分の側面
に形成された窒化ケイ素膜16のみが自己整合的に残る
ことになる。酸化膜14は酸化膜12と同様、p型半導
体基板11に加わる応力を緩和する効果を持っている。
In FIG. 2, the oxide film 14 is formed only in the opening of the p-type semiconductor substrate by thermal oxidation, but CV D (C
hemicat Vapor Deposition )
An oxide film may also be formed on the silicon nitride film 13 by a method. After the silicon nitride film 16 is formed on the entire surface by CVD, it is etched by highly anisotropic dry etching.
If the entire surface is etched, only the silicon nitride film 15 formed on the open bottom part of the p-type semiconductor substrate 11 and the silicon nitride film 13 will be etched, and only the silicon nitride film 16 formed on the sides of the opened part will be etched. will remain in a self-consistent manner. Like the oxide film 12, the oxide film 14 has the effect of relieving stress applied to the p-type semiconductor substrate 11.

ここで、p型半導体基板11を開口した部分の側面にの
み窒化ケイ素膜16を残す効果は水または酸素の横方向
への供給を防いで、横方向への酸化、すなわちbird
’s+ beak  を発生させないことである。水ま
たは酸素は開口された部分の底面部にのみ供給されるの
で、酸化は縦方向にだけ促進される。
Here, the effect of leaving the silicon nitride film 16 only on the side surface of the open portion of the p-type semiconductor substrate 11 is to prevent the lateral supply of water or oxygen, and to prevent lateral oxidation, that is, bird
's+beak should not be generated. Since water or oxygen is supplied only to the bottom of the open section, oxidation is promoted only in the longitudinal direction.

第2図Bは第2図Aの後、選択酸化した状態である01
7は選択酸化によって形成された酸化膜である。コノ時
、bird’s beak 、 bird’s+ he
adはほとんど生じないことを我々は実験によって確認
した。このことは、p型半導体基板11を開口する時、
第1ステツプとして等方的にエツチングし、第2ステツ
プとして異方的にエツチングした後酸化膜14、窒化ケ
イ素膜16を形成していることによってもたらされる。
Figure 2B shows the state of selective oxidation after Figure 2A.
7 is an oxide film formed by selective oxidation. At this time, bird's beak, bird's+ he
We have experimentally confirmed that ad hardly occurs. This means that when opening the p-type semiconductor substrate 11,
This is achieved by isotropically etching as a first step and anisotropically etching as a second step, and then forming the oxide film 14 and silicon nitride film 16.

ここで、2段階のエンチングしている理由は全面ドライ
エツチングによって窒化ケイ素膜15を開口した部分の
側面にのみ残す際、下地酸化膜12の近傍に厚く窒化ケ
イ素膜を残すことによって、bird’s beak 
 を防ぐ効果を有している。
Here, the reason for the two-step etching is that when the silicon nitride film 15 is left only on the side surfaces of the open portion by dry etching the entire surface, by leaving a thick silicon nitride film near the base oxide film 12, the bird's beak
It has the effect of preventing

詳しく説明すると、第1ステツプとしてのp型半導体基
板11を等方的にエツチングするのは、窒化ケイ素膜1
3をオーバーハングさせるためであシ、第2ステツプと
して異方的にエツチングするのは寸法精度良く微細加工
を実現するためである0 ここで、等方的そして異方的にエツチングした後、酸化
膜14、窒化ケイ素膜16を形成する時に、酸化膜14
及び窒化ケイ素膜16はオーバーハングした窒化ケイ素
膜13の下部、すなわちp型半導体基板11のサイドエ
ッチされた部分16に形成されることになる。つまり、
窒化ケイ素膜16はオーバーハングした窒化膜13の端
部より内側に形成されることになる。それ故、窒化ケイ
素膜13と16とによって下地酸化膜12は完全に覆わ
れていることになる。その後、全面を異方性の強いドラ
イエツチングをすると、窒化ケイ素膜13上に形成され
た窒化ケイ素膜及びp型半導体基板を開口した底面部の
窒化ケイ素膜は完全にエツチングされ、開口した穴の側
面部に形成された窒化ケイ素膜の上端部も多少エツチン
グされるが、窒化ケイ素膜13のオーバーハングした端
部より9べ・−゛ 内側に形成されている窒化ケイ素膜はエツチングされな
い。そのため、窒化ケイ素膜13と16とによって下地
酸化膜12は完全に覆われたままであり、下地酸化膜1
2を介して酸素あるいは水は供給されないのでbird
’s beakはほとんど生じない。
To explain in detail, the first step of isotropically etching the p-type semiconductor substrate 11 is to etch the silicon nitride film 1.
This is to overhang the etching layer 3.The second step of anisotropic etching is to realize microfabrication with high dimensional accuracy.After isotropic and anisotropic etching, When forming the film 14 and the silicon nitride film 16, the oxide film 14
The silicon nitride film 16 is formed under the overhanging silicon nitride film 13, that is, on the side-etched portion 16 of the p-type semiconductor substrate 11. In other words,
The silicon nitride film 16 is formed inside the overhanging end of the nitride film 13. Therefore, the base oxide film 12 is completely covered by the silicon nitride films 13 and 16. After that, when the entire surface is subjected to highly anisotropic dry etching, the silicon nitride film formed on the silicon nitride film 13 and the silicon nitride film on the bottom surface where the p-type semiconductor substrate is opened are completely etched, and the opened holes are completely etched. The upper end of the silicon nitride film formed on the side surface is also etched to some extent, but the silicon nitride film formed 9 bases inward from the overhanging end of the silicon nitride film 13 is not etched. Therefore, the base oxide film 12 remains completely covered by the silicon nitride films 13 and 16, and the base oxide film 12 remains completely covered by the silicon nitride films 13 and 16.
Since no oxygen or water is supplied through 2, the bird
's peak rarely occurs.

我々は実験によって、p型半導体基板をドライエツチン
グのみで異方的に開口した場合、及び本発明の特長であ
る等方的、そして異方的に開口した場合更に従来方法と
でbird’s beakの差を比較した。選択酸化に
よって2.0μmの酸化膜を形成した場合、ドライエツ
チングのみで開口した時はbird’s beakは1
.2 p m、 bird’s headは0.5μm
生じているが、等方的そして異方的に開口した場合はb
ird’s beak /do、3 prn、 bir
d’5headは生じていない。従来方法ではbird
’5beakは1.6 p m、 bird’s he
adは1.0μm生じている。従来方法に比べて、我々
が先に提案した方法を用いるとbird’s beak
  は19q6にまで小さくすることができ、bird
’s head は全く生10ベー′ しない効果を持っている。異方的なドライエツチングの
みで開口した場合は、下地酸化膜の近傍に残っている窒
化ケイ素膜が薄いため、選択酸化の途中からbiτd’
s beak  が生じている。
Through experiments, we have found that when a p-type semiconductor substrate is opened anisotropically by dry etching alone, when opened isotropically and anisotropically, which is a feature of the present invention, and when compared with the conventional method, bird's beak The difference was compared. When a 2.0 μm oxide film is formed by selective oxidation, the bird's beak is 1 when the opening is made only by dry etching.
.. 2pm, bird's head is 0.5μm
but if it opens isotropically and anisotropically, b
ird's beak /do, 3 prn, bir
d'5head has not occurred. In the conventional method, bird
'5beak is 1.6 pm, bird's he
ad is 1.0 μm. Compared to the conventional method, using the method we proposed earlier, the bird's beak
can be as small as 19q6, bird
's head has no effect at all. If the opening is formed only by anisotropic dry etching, the silicon nitride film remaining near the underlying oxide film is thin, so biτd'
sbeak is occurring.

本発明者らは上記の如く先に提案した方法がプロセス的
に安定でしかも歩留良く深い絶縁分離酸化膜出来るとい
う点に鑑み、この深い絶縁分離酸化膜直下にチャンネル
ストンパーを形成することにより、チャンネル部分とチ
ャンネルストッパーを実質的に大きく離して狭チャンネ
ル効果を少なくするものである。
In view of the fact that the previously proposed method is process-stable and can produce a deep insulating isolation oxide film with good yield, the present inventors formed a channel stopper directly under this deep insulating isolation oxide film. The channel portion and the channel stopper are substantially separated from each other to reduce the narrow channel effect.

以下、第3図A−Eとともに本発明に係る具体的な製造
方法の一実施例を示す。第3図Aにおいて、21はたと
えばp型半導体基板、22は下地酸化膜で100OA形
成してあり、23はCVD−法により形成された1 0
00Aの窒化ケイ素膜である。24は7オトリソ法によ
りバター二/グされたレジスト膜である。
Hereinafter, an embodiment of a specific manufacturing method according to the present invention will be shown in conjunction with FIGS. 3A to 3E. In FIG. 3A, 21 is, for example, a p-type semiconductor substrate, 22 is a base oxide film formed with a thickness of 100 OA, and 23 is a 10 OA formed by CVD method.
00A silicon nitride film. 24 is a resist film which has been butter-printed by the 7-otolithography method.

このレジスト膜24をマスクとして窒化ケイ素膜23を
ドライエツチングし、それから下地酸化11’、 膜24をエツチングして開口部21aを形成する。
Using this resist film 24 as a mask, the silicon nitride film 23 is dry etched, and then the base oxide 11' and film 24 are etched to form an opening 21a.

この状態の時、レジスト膜24は充分残っている0その
後、レジスト膜24をマスクとしてp型半導体基板21
を0.1μmケミカルエツチングして開口部21bを形
成する。この時、サイドエッチは深さ方向と同じ<0.
1μm生じている。この時のエツチングはケミカルエツ
チングでなく、ドライエツチングでも等方向にエツチン
グされるプラズマエツチングを使っても別に構わない。
In this state, the resist film 24 remains sufficiently. Then, using the resist film 24 as a mask, the p-type semiconductor substrate 21 is
The opening 21b is formed by chemical etching of 0.1 μm. At this time, the side etch is the same as the depth direction <0.
1 μm is generated. The etching at this time is not chemical etching, but may be dry etching or plasma etching which etches in the same direction.

次にレジスト膜24を更にマスクとして、ドライエツチ
ングでも異方性の強い反応性スパッタエツチングあるい
はイオンエツチングによって、垂直にエツチングして開
口部21aを形成する。p型半導体基板21の総エツチ
ング量は0.76μm である。こうして開口部21c
が形成される0 更に、レジスト膜24をマスクとして、p型半導体基板
の開口部を通してS+をイオン注入によって打ち込み、
チャネルストッパー25を形成する0 その後、レジスト膜24を除去し、熱酸化によはp型半
導体基板21を開口した部分にのみ形成され、窒化ケイ
素膜23上には形成されていない。
Next, using the resist film 24 as a mask, the opening 21a is formed by etching vertically by reactive sputter etching or ion etching, which is highly anisotropic even when dry etching is used. The total etching amount of the p-type semiconductor substrate 21 is 0.76 μm. In this way, the opening 21c
Further, using the resist film 24 as a mask, S+ is ion-implanted through the opening of the p-type semiconductor substrate.
Forming the channel stopper 25 After that, the resist film 24 is removed, and by thermal oxidation, the channel stopper 25 is formed only in the open portion of the p-type semiconductor substrate 21, and is not formed on the silicon nitride film 23.

しかし、この酸化膜形成方法はCVD法により全面に形
成しても別に構わない。その後、全面に窒化ケイ素膜2
7を1000A形成する(第3図B)。
However, this oxide film formation method may be performed by CVD method to form the entire surface. After that, a silicon nitride film 2 is applied to the entire surface.
7 to form 1000A (FIG. 3B).

第3図Cにおいては、異方性の強いドライエツチングで
ある反応スバノタエノテングあるいはイオンエツチング
によって、全面エツチングする。
In FIG. 3C, the entire surface is etched by reactive etching or ion etching, which is highly anisotropic dry etching.

このエツチングの時、異方性が強いため縦方向にはエツ
チングされるが、横方向にはエツチングされないため、
開口した部分の側面に形成された窒化ケイ素膜27′の
みが自己整合的に残ることになるO その後、選択酸化することによって酸化膜28を1.6
μm形成する。この酸化は高圧酸化を用いれば1ooo
℃、6.5 Kg / c−の条件で約90分と短い時
間で酸化ができる。
During this etching, because the anisotropy is strong, it is etched in the vertical direction, but not in the horizontal direction, so
Only the silicon nitride film 27' formed on the side surface of the opening remains in a self-aligned manner. Thereafter, selective oxidation is performed to reduce the oxide film 28 to 1.6
μm is formed. This oxidation can be reduced to 1ooo using high pressure oxidation.
Oxidation can be carried out in a short time of about 90 minutes under the conditions of ℃ and 6.5 kg/c-.

このような方法によれば、bird’s beak  
はほとんどなく、高密度かつ高精度でフィールド酸化1
3べ 膜を従来に比べ、2倍程度深く形成することができる(
第3図D)0 第3図Eはフィールド酸化終了後、通常のMOSプロセ
スでトランジスタを形成した状態である。
According to such a method, bird's beak
field oxidation1 with high density and high precision.
The 3-layer membrane can be formed approximately twice as deep as conventional methods (
FIG. 3D)0 FIG. 3E shows a state in which a transistor is formed by a normal MOS process after field oxidation.

29はゲート酸化膜、30はpotySi  ゲート、
31はソース、31′はドレインである。32は配線用
のCVD法による酸化膜、33はAt配線である。
29 is a gate oxide film, 30 is a potySi gate,
31 is a source, and 31' is a drain. 32 is an oxide film for wiring formed by CVD method, and 33 is At wiring.

以上述べてきたように、本発明はシリコン基板を開口し
た部分の側面にのみ窒化ケイ素膜を安定に残すことによ
って、選択酸化時に生じるbird’5beak を極
力減少させ、bird’s headは全く生じないと
いう効果を持っている。bird’s beakを最大
限防いでいることにより、トランジスタの活性領域のつ
ぶれは非常に少なくなり、高密度化。
As described above, the present invention minimizes the bird's 5beak that occurs during selective oxidation by leaving a silicon nitride film stably only on the side surfaces of the open portion of the silicon substrate, and no bird's head occurs at all. It has this effect. By preventing bird's beak to the maximum extent possible, collapse of the active region of the transistor is extremely reduced, resulting in higher density.

高精度化に寄与している(、 bird’s head
は全く生じないため、シリコン基板表面は平坦で、At
配線時における段差部での断線あるいはエッチ残りによ
る短絡もおこらず、プロセスが安定しているため歩留の
向上につながっている。
Contributes to high precision (bird's head
Since At does not occur at all, the silicon substrate surface is flat and At
There are no disconnections at stepped portions during wiring or short circuits due to etch residue, and the process is stable, leading to improved yields.

14″− しかも、bird’s beakがほとんどなく、非常
に深いフィールド酸化膜を形成できるので、チャネル・
ストッパーも深く形成される。そのため拡散によりチャ
ネル・ストッパーが広がってもチャネル部には何の影響
を与えないので、狭チャネル効果を防ぐことができ、チ
ャネル幅が短くなってもvthの変動は非常に小さくな
る。したがって、非常に高密度、高精度で、狭チャネル
効果のない微細なMoS半導体装置の実現が可能になる
。本発明においてシリコン基板の等方向エツチングは0
.1μmに限らず、もう少し大きく、あるいは小さくし
ても、同等の効果を有することも確認している。
14"- Moreover, there is almost no bird's beak and a very deep field oxide film can be formed, so the channel
The stopper is also formed deeply. Therefore, even if the channel stopper widens due to diffusion, it does not have any effect on the channel portion, so the narrow channel effect can be prevented, and even if the channel width becomes short, the variation in vth becomes extremely small. Therefore, it becomes possible to realize a fine MoS semiconductor device with extremely high density and high precision, and without narrow channel effects. In the present invention, the isodirectional etching of the silicon substrate is 0.
.. It has also been confirmed that the same effect can be obtained even if the thickness is not limited to 1 μm, but is slightly larger or smaller.

以上のように本発明は高密度、高精度で狭チャネル効果
のないMoS半導体装置の製造方法に大きく寄与し、ま
た工業的にも非常に価値の高いものである。
As described above, the present invention greatly contributes to a method for manufacturing a MoS semiconductor device with high density, high precision, and no narrow channel effect, and is also of great industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のMoS半導体装置の構造断面図、第2図
は先に提案した半導体装置の製造方法を示す工程断面図
、第3図(8)〜(6)は本発明の一実施例にかかる半
導体装置の要部製造工程図である。 2.26・・・・・・チャネル・ストッパー、16・・
・・−・・等方的なエツチングによりサイドエツチング
された部分、14.26・・・・・酸化膜、15゜27
′・・・・・・シリコン基板を開口した部分の側面にの
み残っている窒化ケイ素膜、17.28・・・・・・選
択酸化により形成されたフィールド酸化膜、11’  
21 a  21 b  2 I C””:r−ッチン
グによる開口部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名?? 匍 3 図 230
FIG. 1 is a structural cross-sectional view of a conventional MoS semiconductor device, FIG. 2 is a process cross-sectional view showing the previously proposed method for manufacturing a semiconductor device, and FIGS. 3 (8) to (6) are an embodiment of the present invention. FIG. 3 is a manufacturing process diagram of main parts of the semiconductor device according to the present invention. 2.26...Channel stopper, 16...
・・・・・・Part side-etched by isotropic etching, 14.26・・・・Oxide film, 15°27
'...Silicon nitride film remaining only on the side surface of the opening in the silicon substrate, 17.28...Field oxide film formed by selective oxidation, 11'
21 a 21 b 2 I C"": Opening by r-etching. Name of agent: Patent attorney Toshio Nakao and one other person? ? Sword 3 Figure 230

Claims (1)

【特許請求の範囲】[Claims] (1)一方導電型半導体領域上に第1の絶縁膜及び第2
の絶縁膜を形成する工程と、前記第2及び第1の絶縁膜
を開口する工程と、前記第1の絶縁膜の端部より前記一
方導電型半導体領域を等方的に開口する工程と、前記第
1の絶縁膜を開口した領域を介して、前記一方導電型半
導体領域を、前記等方的に開口した領域よりも内側に深
く開口する工程と、前記第1の絶縁膜を開口した領域を
介して、前記一方導電型半導体領域に一方導電型半導体
層を形成する工程と、少くとも前記一方導電型半導体領
域を開口した領域に第3の絶縁膜を形成する工程と、前
記第1.第2の絶縁膜及び前記第1、第2の絶縁膜及び
前記一方導電型半導体領域を開口した領域の側面部にの
み第4の絶縁膜を形成する工程と、前記一方導電型半導
体層に接するまで、前記一方導雷創半導体領域を酸化す
る工程2べ一7゛ とを備えたことを特徴とする半導体装置の製造方法0
(1) A first insulating film and a second insulating film are formed on one conductivity type semiconductor region.
forming an insulating film; opening the second and first insulating films; opening the one conductivity type semiconductor region isotropically from an end of the first insulating film; opening the one-conductivity type semiconductor region deeper inside than the isotropically opened region through the region where the first insulating film is opened; and the region where the first insulating film is opened. a step of forming a one conductivity type semiconductor layer in the one conductivity type semiconductor region via the first conductivity type semiconductor region; a step of forming a third insulating film in a region opening at least the one conductivity type semiconductor region; forming a fourth insulating film only on the side surface of the second insulating film, the first and second insulating films, and a region where the one conductivity type semiconductor region is opened; and a fourth insulating film in contact with the one conductivity type semiconductor layer. A method for manufacturing a semiconductor device 0, characterized in that it comprises step 2 of oxidizing the one lightning-induced semiconductor region.
JP2624582A 1981-12-08 1982-02-19 Manufacture of semiconductor device Pending JPS58142541A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2624582A JPS58142541A (en) 1982-02-19 1982-02-19 Manufacture of semiconductor device
US06/660,255 US4563227A (en) 1981-12-08 1984-10-12 Method for manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2624582A JPS58142541A (en) 1982-02-19 1982-02-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58142541A true JPS58142541A (en) 1983-08-24

Family

ID=12187903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2624582A Pending JPS58142541A (en) 1981-12-08 1982-02-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58142541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4968636A (en) * 1988-09-14 1990-11-06 Oki Electric Industry Co., Ltd. Embedded isolation region and process for forming the same on silicon substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4968636A (en) * 1988-09-14 1990-11-06 Oki Electric Industry Co., Ltd. Embedded isolation region and process for forming the same on silicon substrate

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