JPS58141629U - oscillation circuit - Google Patents
oscillation circuitInfo
- Publication number
- JPS58141629U JPS58141629U JP3783782U JP3783782U JPS58141629U JP S58141629 U JPS58141629 U JP S58141629U JP 3783782 U JP3783782 U JP 3783782U JP 3783782 U JP3783782 U JP 3783782U JP S58141629 U JPS58141629 U JP S58141629U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- output
- input terminal
- oscillation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案発振回路の回路構成図であり、第２図は
第１図の発振回路におけるタイムチャート示す。
ＯＳＣ・・・・・・基準信号源、ＦＦ１・・・・・・第
１のフリップ・フロップ、ＦＦ２・・・・・・第２のフ
リップ・フロップ。FIG. 1 is a circuit diagram of the oscillation circuit of the present invention, and FIG. 2 is a time chart of the oscillation circuit of FIG. OSC: Reference signal source, FF1: First flip-flop, FF2: Second flip-flop.
Claims (1)
Ｆ１の入力端子Ｃ１と第２のフリップ・フロップＦＦ２
の入力端子Ｃ２に接続し、前記第１のフリップ・フロッ
プＦＦ１の出力Ｑ１を前記第２のフリップ・フロップＦ
Ｆ２の入力端子Ｄ２と接続し、前記第２のフリップ・フ
ロップＦＦ２の出力Ｑ２を前記第１のフリップ・フロッ
プＦＦ□の入力端子Ｄ１と接続し、さらに前記第１のフ
リップ・フロップＦＦ工の出力Ｑ□もしくはＱｌあるい
は第２のフリップ・フロップＦＦ２の出力Ｑ２もしくは
Ｑ２から外部出力信号を ° 。 とり出すように構成したことを特徴とする発振回路。[Claims for Utility Model Registration] The output of the reference signal source O8C is connected to the first flip-flop F.
Input terminal C1 of F1 and second flip-flop FF2
is connected to the input terminal C2 of the first flip-flop FF1, and the output Q1 of the first flip-flop FF1 is connected to the input terminal C2 of the second flip-flop F
F2, the output Q2 of the second flip-flop FF2 is connected to the input terminal D1 of the first flip-flop FF□, and the output of the first flip-flop FF is connected to the input terminal D2 of the second flip-flop FF2. An external output signal is output from Q□ or Ql or the output Q2 or Q2 of the second flip-flop FF2. An oscillation circuit characterized in that it is configured to be extracted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3783782U JPS58141629U (en) | 1982-03-19 | 1982-03-19 | oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3783782U JPS58141629U (en) | 1982-03-19 | 1982-03-19 | oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58141629U true JPS58141629U (en) | 1983-09-24 |
Family
ID=30049204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3783782U Pending JPS58141629U (en) | 1982-03-19 | 1982-03-19 | oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58141629U (en) |
-
1982
- 1982-03-19 JP JP3783782U patent/JPS58141629U/en active Pending
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