JPS58140803A - Process controller - Google Patents

Process controller

Info

Publication number
JPS58140803A
JPS58140803A JP2263182A JP2263182A JPS58140803A JP S58140803 A JPS58140803 A JP S58140803A JP 2263182 A JP2263182 A JP 2263182A JP 2263182 A JP2263182 A JP 2263182A JP S58140803 A JPS58140803 A JP S58140803A
Authority
JP
Japan
Prior art keywords
control
memory
process controller
control calculation
ecc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2263182A
Other languages
Japanese (ja)
Inventor
Tsutomu Sakamaki
坂巻 勤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2263182A priority Critical patent/JPS58140803A/en
Publication of JPS58140803A publication Critical patent/JPS58140803A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00Safety arrangements
    • G05B9/02Safety arrangements electric
    • G05B9/03Safety arrangements electric with multiple-channel loop, i.e. redundant control systems

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To obtain a process controller of double structure which has a simple and assured operation, by combining two control arithmetic parts, a memory containing an error correcting function and a switch control part. CONSTITUTION:Control arithmetic parts 1A and 1B, a switch control part 7, an input/output part 4 and a controlled system 5 are formed centering on a memory 8 containing an ECC. The memory 8 stores all kinds of information necessary for control. As error of the memory 8, if arises while the part 1A is under a control operation, produces no problem to continue the control as long as it is within a correctable range. In case the part 1A has a fault, the part B is connected to the memory 8 by the control part 7. Thus the part 1B continues the control operation on the basis of the contents of the memory 8. As a result, a double-structure process controller having a simple and assured operation can be obtained.

Description

【発明の詳細な説明】 本発明は、プロセス制御装置に係り、特に、制御の履歴
が問題となるシーケンス制御を含むプロセス制御装置の
構成に関するものである・従来のプロセス制御装置にお
いては、特に信頼性を要求される場合は多重化(その多
くは2重化)されて構成されるのが一般的である。第1
図および! 211t;jその構成例の2つを示す図で
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process control device, and in particular to the configuration of a process control device including sequence control in which control history is a problem. When high performance is required, it is common to configure multiplexed (in most cases duplex) configurations. 1st
Figures and! 211t;j is a diagram showing two examples of its configuration.

第1図は、共通メモリ3t−用いてA、Br1i制御系
を結びつけ、例えばA制御系が故障の場合には制御の途
中の情報(例えばどこまで演算したかなど)を共通メモ
リ3に侵す様なソフトウェア構成とし、B制御系はこの
情報を基にしそ制御を実行する。ここで、各部の動作を
AIItlJm系が動作していてB制御系に移った場合
について説明する。
In Figure 1, the A and Br1i control systems are connected using a common memory 3t, and if, for example, the A control system fails, information in the middle of the control (for example, how far the calculation has been performed) will be stored in the common memory 3. The system is configured as software, and the B control system executes attack control based on this information. Here, the operation of each part will be described in the case where the AIItlJm system is operating and the control system is shifted to the B control system.

へ制御系は制御演算部IA、専用メモIJ 2 Aから
なり、制御演算部IAは専用メモIJ 2 Aに入って
いるt&!I N情報(いわゆるプログラム]に基づい
て入出力部4を通して制御対象5に対して1tilJ御
動作を行う。この時に、例えば演算途中の情報など、履
歴が必要な情報は新たな演算結果が得られるたびに共通
メモリ3に格納しておく。この様な状態で、XOす御演
11t部IAに故障が生じたとすると、その結果は診断
lW報11Aとして切替制御部7に伝えられる。切替・
11jtiL1部7はその情報を基に1fflJ御演算
部IAによる制御を制御演算部IBによる制御へ切替え
る操作を行う。制御演算mlBは、専用メモリ2BCl
用メモリIAと同一内容が格納されている)と共通メモ
リ3の情報により制御対象3 &(対して、人出力部4
を通して制m@作を行う。
The control system consists of a control calculation section IA and a dedicated memo IJ2A, and the control calculation section IA is contained in the dedicated memo IJ2A. A 1tilJ control operation is performed on the controlled object 5 through the input/output unit 4 based on the I/N information (so-called program).At this time, a new calculation result is obtained for information that requires a history, such as information in the middle of calculation. It is stored in the common memory 3 every time.In such a state, if a failure occurs in the XO control section IA, the result is transmitted to the switching control section 7 as a diagnostic IW report 11A.
Based on the information, the 11jtiL1 unit 7 performs an operation to switch the control by the 1fflJ control calculation unit IA to the control by the control calculation unit IB. Control calculation mlB is executed in dedicated memory 2BCl
The same contents as the memory IA are stored in the control target 3 & (in contrast, the human output unit 4
Control m @ production through.

この様にして、いずれかの制御演算部にトラブルが生じ
九場合でも所定の制■動作を続行するεとができる。
In this way, it is possible to continue the predetermined control operation even if trouble occurs in any of the control calculation units.

第2図の場合もほぼ同一の構成であるが、第1図の場合
と異なり、共通メモリ3が通信装置6に置換されている
。この第2図の場合は、共通メモI73に記憶すべき履
歴情報をただちに通信回線6を通じて一方の制御系の専
用メモリに送っておくようKするもので、共通メモリを
それぞれ専用メモリIAとIBとに分けて持つ様にした
ものと等価であり、第1図と同様に、いずれかの制御演
算部IAまたはIBに故障が生じ次場合は一方の制御系
で制御を続けることができる。
The configuration shown in FIG. 2 is almost the same, but unlike the case shown in FIG. 1, the common memory 3 is replaced by a communication device 6. In the case of FIG. 2, the history information to be stored in the common memo I73 is immediately sent to the dedicated memory of one control system via the communication line 6, and the common memory is divided into dedicated memories IA and IB, respectively. Similarly to FIG. 1, if a failure occurs in either control calculation section IA or IB, control can be continued with one control system.

しかし、このような構成においては、メモリがハードウ
ェア的に2〜3個に分割されているため、構成が複雑に
なると同時に、例えば制御プログラムを専用メモリIA
とIBとの両方に格納しておく必要がある。この仁とは
、プログラムの格納、fly、パラメータの設定、変更
時には両方のメモリの内容を常に同じ様にしておかなけ
ればならないことを意味し、取扱いが複雑になる欠点が
ある。
However, in such a configuration, the memory is divided into two or three pieces in terms of hardware, which makes the configuration complicated.
It is necessary to store both the data and the IB. This reliability means that the contents of both memories must always be the same when storing or flying a program, or setting or changing parameters, which has the disadvantage of complicating handling.

を几、第1図の場合は、ノ・−ドウエア的に2種のメモ
リが必要となり、一方2図の場合はA、B制御系が常時
過信を行う必要があり、いずれもシステム構成が複雑に
なるという欠点がある。
In the case of Fig. 1, two types of memory are required in terms of hardware, while in the case of Fig. 2, the A and B control systems need to be constantly overconfident, and the system configuration is complicated in both cases. It has the disadvantage of becoming

本発明の目的は、構成が簡単で、かつ動作が確実な2重
化されたプロセス制御装置を提供することにある。
An object of the present invention is to provide a redundant process control device that is simple in configuration and reliable in operation.

従来、制御装置のバックアップの考え方の一つに、故障
する部分を多重化(多くは2重化)して制御の動作を続
行するという考えがある。逆の言い方をすれば、故障し
ない部分はバックアップする必要がない、そこで、本発
明け、従来から問題の多かつ九メモリ部にエアー訂正付
メモリ(以下ECC付メモリと称する)t−用い、−重
故障に対してはメモリのバックアップを考えないで曳い
という考え方に立ち、制御演算部のみを2重化するとい
う考えをとり、簡単な構成で、有効な2重化プロセス制
@装置を構成したものである。つまり、自分自身で修復
が可能な部分はそれ自身でカックーし、それが不可能な
部分のみを2重化するという考え方に基づきプロセス制
御装置を構成したものである。
Conventionally, one of the ideas for backing up a control device is to multiplex (in many cases, duplicate) a failed part and continue control operations. In other words, there is no need to back up parts that do not fail.Therefore, the present invention uses a memory with air correction (hereinafter referred to as memory with ECC) in the memory section, which has had many problems in the past. Based on the idea of not considering memory backup in case of a major failure, we took the idea of duplicating only the control calculation section, and created an effective duplex process @ device with a simple configuration. It is something. In other words, the process control device is constructed based on the idea that parts that can be repaired by themselves will be self-repaired, and only parts that cannot be repaired will be duplicated.

以下第3図、第4図により本発明を実施例に基づき説明
する。
The present invention will be explained below based on examples with reference to FIGS. 3 and 4.

第3図は本発明の一実施例を示す構成図であり、第4図
はバスの切替えを説明するために要部を抜きだしたもの
である。
FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 shows the main parts extracted to explain bus switching.

これらの図においてECC付メモリ8を中心圧して、制
御演算部IA、IB、切替制御部7、入出力部4、制御
対象5から構成されている。 ECC付メモリ8には制
御に必要な全ての情報(プログラム、パラメータ、演算
途中結果など)が格納されている。いま制御演算部IA
が制御演算を行っているとする。この場合、ECC付メ
モリ8にエラーを生じても訂正可能範囲内(例えば、1
ビツトエラー修復、2ビツトエラー検出の場合は1ビツ
トエラーが発生)であれば、例えばアラームを発生させ
るのみで制御の続行上は何の間頓も生じない0間yII
IFi演算制御部IAに故障が生じ九場合である。この
場合、診断清報11Aに基づいて、切替制御部7は切替
信号14Aにより制御演算部IAtメモリバス9から切
離し、切替信号14Bにより制御演算部IBtメモリバ
ス9に接続する。
In these figures, the system is composed of control calculation sections IA and IB, a switching control section 7, an input/output section 4, and a controlled object 5, with the memory 8 with ECC as the center. The memory with ECC 8 stores all information necessary for control (programs, parameters, intermediate results of calculations, etc.). Now control calculation unit IA
Suppose that is performing control calculations. In this case, even if an error occurs in the ECC memory 8, it is within the correctable range (for example, 1
If the bit error is repaired or a 1-bit error occurs when a 2-bit error is detected, for example, the 0-time yII will only generate an alarm and will not cause any interruption in the continuation of control.
This is a case where a failure occurs in the IFi calculation control unit IA. In this case, based on the diagnostic report 11A, the switching control unit 7 is disconnected from the control calculation unit IAt memory bus 9 by the switching signal 14A, and connected to the control calculation unit IBt memory bus 9 by the switching signal 14B.

これにより、制御演算部IBは全ての制(資)情報を格
納しているECC付メモリ8の内容に従って制御演算を
継続することができる。
This allows the control calculation section IB to continue the control calculation according to the contents of the ECC memory 8 that stores all control information.

第4図は制御演算部IA、IBとECC付メモリ8との
接続方法の例を示したもので、制御演算部IA、IBの
出力データ12A、12Bのみ會切替信号14A、14
Bにより出力ゲー)13A。
FIG. 4 shows an example of the connection method between the control calculation units IA and IB and the memory with ECC 8, in which only the output data 12A and 12B of the control calculation units IA and IB are connected to the party switching signals 14A and 14.
Output game by B) 13A.

13Bにより制御するようにしたものである。13B.

このように本実施例によれば、1つのECC付メモリ8
を用いるのみで2つの制御演算部の切替えが行なえ、第
1および2図に示した従来方法と比較して次のような特
有の効果がある。すなわち、(1)メモリについてのバ
ックアップを考える必要がなくなり、制御演算部のみバ
ックアップすればよく、ノ・−ドウエア構成が簡単にな
る。
In this way, according to this embodiment, one memory with ECC 8
It is possible to switch between the two control calculation units only by using , and compared with the conventional method shown in FIGS. That is, (1) there is no need to think about backing up the memory, and only the control calculation section needs to be backed up, which simplifies the hardware configuration.

(2)制御系の切替時にも、またプログラムの変更時に
4ただ1つのメモリを考えて行えばよく、従来方法の様
に常に2つ以上のメモリを考える必要がなくなり、ソフ
トウェアも簡単になる。
(2) When switching control systems or changing programs, it is only necessary to consider only one memory, which eliminates the need to always consider two or more memories as in the conventional method, and the software becomes simpler.

以上の説明から明らかなように本発明によれば、プロセ
ス制御装置のバックアップを制御演算部のみに限定する
ことができるため、以下の効果がある。すなわち、メモ
リを1種類のみしか使用しないため、システム構成が簡
単となり、ハード、ソフト両面からの取扱いが簡単とな
る。特に、制御清報を含めた全ての情報が一つのメモリ
内にあるため、制御演算の受渡しが極めて明確である。
As is clear from the above description, according to the present invention, the backup of the process control device can be limited to only the control calculation section, so that the following effects can be achieved. That is, since only one type of memory is used, the system configuration is simplified and handling from both hardware and software aspects is simplified. In particular, since all information including control information is stored in one memory, the transfer of control calculations is extremely clear.

また、待機系制御演算は、常にイニシャル状態から奥行
を開始すれば良い、釘に、制御演算部にマイク曽プ1セ
ッサが使用されることが多いが、出力信号のみを切替え
ればよく、マイクロプロセッサのアーキテクチャに依存
しない切替え方法が使える等極めて有効な幼果が得られ
る。
In addition, for standby control calculations, it is sufficient to always start the depth from the initial state.In addition, although a microphone processor is often used in the control calculation section, it is only necessary to switch the output signal. Very effective results can be obtained, such as the ability to use a switching method that does not depend on processor architecture.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来装置のブロック図、第3図は
本発明の一実施例を示すブロック図、第4図は上記実施
例の要部を示すブロック図である。 1A、IB・・・制御演算部、2A、2B・・・専用メ
モリ、3・・・共用メモリ、7・・・切替制御部、8・
・・FCC第 1 目 第 2 図 茅3 図 7 第4目
1 and 2 are block diagrams of a conventional device, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing the main parts of the above embodiment. 1A, IB... Control calculation unit, 2A, 2B... Dedicated memory, 3... Shared memory, 7... Switching control unit, 8.
...FCC No. 1 No. 2 Fig. 3 Fig. 7 No. 4

Claims (1)

【特許請求の範囲】[Claims] 1、 2つの制御演算部と、1つのエラー訂正機能付メ
モリと、切替制御部とからなり、制御に関する全ての情
報を上記エラー訂正機能付メモリに格納し、制御演算部
、メモリに故障が生じて4制御演算を連続して行うこと
を特徴とするプロセス制#装置。
1. It consists of two control calculation units, one memory with an error correction function, and a switching control unit, and all information related to control is stored in the memory with an error correction function, and if a failure occurs in the control calculation unit or the memory. A process control device characterized by continuously performing four control calculations.
JP2263182A 1982-02-17 1982-02-17 Process controller Pending JPS58140803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2263182A JPS58140803A (en) 1982-02-17 1982-02-17 Process controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2263182A JPS58140803A (en) 1982-02-17 1982-02-17 Process controller

Publications (1)

Publication Number Publication Date
JPS58140803A true JPS58140803A (en) 1983-08-20

Family

ID=12088168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2263182A Pending JPS58140803A (en) 1982-02-17 1982-02-17 Process controller

Country Status (1)

Country Link
JP (1) JPS58140803A (en)

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