JPS5814069A - Acceleration test of electro-migration - Google Patents
Acceleration test of electro-migrationInfo
- Publication number
- JPS5814069A JPS5814069A JP56111853A JP11185381A JPS5814069A JP S5814069 A JPS5814069 A JP S5814069A JP 56111853 A JP56111853 A JP 56111853A JP 11185381 A JP11185381 A JP 11185381A JP S5814069 A JPS5814069 A JP S5814069A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- film
- wiring film
- test
- test sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体基板上に形成した金属配線膜のエレク
トロマイグレーションの加速試験方法に関する。半導体
集積回路は、近時高集積化ならびに高密度化の方向にあ
り、回路パターン寸法の微M化が進行している。このよ
うなパターン寸aの微細化に伴い、回路構成素子などの
電気的特性との関連において、構造、配置及び加工プロ
セスなどに大きな変革を受けつつある。各構成素子間を
電気的相互接続する金属配線膜についても寸法微細化に
伴い各種の問題が生じている。特に金属配線膜のいわゆ
るエレクトロマイグレーションニよる配線抵抗の増加あ
るいけ断線は、寸法微細化とともにクローズアップされ
た大きな問題点の一つである。ところで高集積化を進め
るに際17てr」、金属配線膜を多層とする所謂多層l
lk!線J117i造も必要となり、多層配線構造をも
含めた金kJ′!配線膜のエレクトロマイグレーション
現象の定+71化が必要となっている。かかる定]■化
のだめの試験としてエレクトロマイグレーション加速試
験がある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for accelerating electromigration testing of a metal wiring film formed on a semiconductor substrate. 2. Description of the Related Art Semiconductor integrated circuits have recently become highly integrated and densely packed, and circuit pattern dimensions are becoming smaller. With such miniaturization of the pattern size a, the structure, arrangement, processing process, etc. are undergoing major changes in relation to the electrical characteristics of circuit components and the like. Various problems have also arisen with the miniaturization of the dimensions of metal wiring films that electrically interconnect the constituent elements. In particular, an increase in wiring resistance or breakage due to so-called electromigration of a metal wiring film is one of the major problems that has come into focus as dimensions become finer. By the way, as we move towards higher integration, so-called multi-layer metal wiring films are being developed.
lk! Wire J117i structure is also required, and gold kJ' including multilayer wiring structure is also required! It is necessary to stabilize the electromigration phenomenon of wiring films. There is an accelerated electromigration test as a test to prevent such changes.
従来のエレクトロマイクレージ−jンの加速試験では、
高温中で目的とする金1ryl lli:線tl、11
4にのみ電流を流して測定する方法が採られている。こ
のような配線構成試料を用いる試験では、断線に到る捷
でに比較的長時間を要するばかりでなく、゛(勺0体集
積回路装置で実施される名神111線11す1成の実体
と著しく異なるなどの欠点があった。未発[月は、上記
欠点の排除を意図してなさ)またもので、配線膜のエレ
クトロマイクレージiJシの試験時間の短縮と実使用状
態に対応できる加速試験のだめの配線構成を有する試験
状1’lあるいIf、J2、実際に;製作された半導体
装置において特定の関係が成)′Lしている配線部分を
用いる試験方法を捉イノ(するものである。In the conventional electromicrage acceleration test,
Target gold 1ryl lli at high temperature: line tl, 11
A method is adopted in which a current is passed only through 4. In tests using such wiring configuration samples, not only does it take a relatively long time to reach disconnection, but it also takes a relatively long time to reach a disconnection. There were drawbacks such as significant differences.Unexpected [Month was not intended to eliminate the above drawbacks] Also, it was possible to shorten the test time of the electromicrometer iJ for wiring membranes and accelerate it to correspond to actual usage conditions. Test sample 1'l or If, J2, which has a wiring configuration that is not tested, is an innovation that captures a test method using a wiring part that actually has a specific relationship in a manufactured semiconductor device. It is.
かかる本発明のエレクト17マイグレーシコンの加速試
験方法の特徴は、基板上に形成された被試験用の第1の
金属配線膜に電流を流すとともに、同第1の金属配線膜
に近接配置された第2の金属配線膜に電圧を印加するか
もしくけ電流を流し、この状態を保持させるところにあ
る。ところで、このような加速試験を行うに際しては、
上記のように、基板上に第1および第2の金属配線膜が
近接して配置されている配線構造の試験試料を準備する
必要がある。このためには、このような関係を成立させ
た試験試料を製作するか、あるいけ配線部分にこのよう
な関係が成立している半導体装置を用いるかのいずれか
を選択すればよい。The feature of the accelerated testing method for the Elect-17 migration silicon of the present invention is that a current is passed through a first metal wiring film to be tested formed on a substrate, and a metal wiring film placed close to the first metal wiring film is This state is maintained by applying a voltage to the second metal wiring film to cause a current to flow therethrough. By the way, when conducting such accelerated tests,
As described above, it is necessary to prepare a test sample having a wiring structure in which first and second metal wiring films are disposed close to each other on a substrate. For this purpose, it is sufficient to select either to manufacture a test sample in which such a relationship is established, or to use a semiconductor device in which such a relationship is established in the interconnection portion.
第1図は、本発明で使用する試験試料の1例として製作
した立体交差形の配線構造をもつ試験試料を示す図であ
り、図中、1はシリコン基板、2および3けリンガラス
膜あるいは窒化シリコン膜等の絶縁膜、4は例えば被試
験用となるアルミニウム(Aβ)膜、5はAβ膜4とは
絶縁膜3によって絶縁され、しかもAjllll莞4と
立体的に交差するA4膜である。FIG. 1 is a diagram showing a test sample having a three-dimensional intersection wiring structure manufactured as an example of a test sample used in the present invention. In the figure, 1 is a silicon substrate, 2 and 3 are phosphor glass films or An insulating film such as a silicon nitride film, 4 is an aluminum (Aβ) film to be tested, and 5 is an A4 film which is insulated from the Aβ film 4 by the insulating film 3 and also three-dimensionally intersects with the Ajllll ring 4. .
坊、上のような配線44/i造をもつ試験状1”lを用
いる本発明のエレクトロマイグレーシコンの加速試験は
、A l ll+J aに所定の定電流を流すとともに
、Ad暎已に対して所定の電「Fを印加するか、あるい
け、所定の電流を流しこの状態を保持する条件の下で行
われる。In an accelerated test of the electromigration silicon of the present invention using a test specimen 1"l having the wiring 44/i structure as shown above, a predetermined constant current is applied to A l ll + J a, and This is done under the conditions of applying a predetermined voltage F or flowing a predetermined current to maintain this state.
第2図は、かかる本発明のエレクトロマイグレーション
の加速試験方法を定性的に説1列するため模式図であり
、図示するように、被試験用の第1の金属配線膜である
ムe膜4に近接して配置された第2の金属配線膜である
A l l’、’45に例えば電圧が印加されでいるこ
とに」:す、A(9膜4の中のムeイオン(Ajll+
)に対して主部による電界効果などの影響が及ぶ。この
ため、A5イオン流が人l暎4の中を偏って移動するこ
と、あるいは特定の場所において高イオン密度となるこ
となどの不均一な移動が生じる。このことに」二ツて、
人lイオン流が均一である場合にくらべ、断線に到る時
間が短くなる。なお、図中6目、ApHl+ 4に作石
する一気力線、捷た、第2図(b)の矢印7 fqJ:
A (l Ifの4の中の14イオンの流束を示し、
A/膜5と対向する部分8におけるA/イオンの流束が
影響を受けている。FIG. 2 is a schematic diagram for qualitatively explaining the electromigration accelerated test method of the present invention. For example, a voltage is applied to A l l', '45, which is the second metal interconnection film disposed close to A (9).
) is affected by electric field effects due to the main part. This causes non-uniform movement of the A5 ion flow, such as uneven movement of the A5 ion flow within the body 4 or high ion density at specific locations. Two things about this.
Compared to the case where the ion flow is uniform, the time required to reach disconnection is shorter. In addition, the 6th line in the figure, the line of force that forms the stone at ApHL+ 4, is twisted, and the arrow 7 fqJ in Figure 2 (b):
A (l indicates the flux of 14 ions in 4 of If,
The flux of A/ions in the portion 8 facing the A/membrane 5 is affected.
かかるメカニズムを考慮した断線寿命の定性式を次式に
示す。A qualitative formula for the disconnection life considering this mechanism is shown in the following formula.
ここでMTBF: mean time betwee
n failureJ :電流密度 (A/lU )
■ =池の配線膜への印加電圧
α:配線膜と池の配線膜の距離
ε :中間物質の誘電率
φ:活性化エネルギー
第3図は、以」二説り1してきた本発明のエレクトロマ
イグレーションの加速試験方法と従来の加速試験方法と
の試験時間の比較実験の結果を示す図である。この比較
実験では、試験試料として第1図で示す立体交差形の試
料をエポキシ樹脂で封止成型したものを製作して用いた
。Here MTBF: mean time between
nfailureJ: Current density (A/lU) ■ = Applied voltage to the interconnection film α: Distance between the interconnection film and the interconnection film ε: Dielectric constant of the intermediate material φ: Activation energy Figure 3 is as follows. FIG. 2 is a diagram showing the results of an experiment comparing the test time between the electromigration accelerated test method of the present invention and the conventional accelerated test method, which have been discussed in two ways. In this comparative experiment, a sample in the shape of a three-dimensional intersection shown in FIG. 1 was sealed and molded with epoxy resin and used as a test sample.
ところで、試験試料の寸法等の製作条件は次の、通りで
ある。By the way, the manufacturing conditions such as the dimensions of the test sample are as follows.
AjllIり4 (試験用)
素桐:純アルミニウノ1.11ヴリI?:2μ7n膜幅
:15μm
人e膜6
素桐:81を1〜2重j71%IA襄加1.たアルミニ
ウム
膜厚: o、 8 μ?+1 IN 1lV1i ;
15 p 、n絶縁膜3
膜厚が1μmのリンガラス(PSG)膜才た、比較のた
めの加速試験Q;1.1600Cの高温中に試験試料を
20個配置1qシ、内10個についてはA4+1匁4の
電流密度を3.6 X 105A/−に設定するととも
に、kl膜5には電Ll:を印加せず(従来方法)、残
る10個にはA7!11944の電流密度を同一に設定
するとともにA4膜6に30vの直流電圧を印加しく本
発明の方法)、画状Flに故障(断線)が発生する時間
を測定して行った。AjllIri 4 (for exam) Sutou: Pure Aluminum Uno 1.11 Vri I? :2μ7n Membrane width: 15μm human e membrane 6 paulownia: 81 1-2 layers j71% IA 1. Aluminum film thickness: o, 8 μ? +1 IN 1lV1i;
15 p, n insulating film 3 Phosphorous glass (PSG) film with a film thickness of 1 μm. Accelerated test for comparison Q: 1. 20 test samples were placed in a high temperature of 1600 C, 1 q, of which 10 were The current density of A4+1 momme 4 was set to 3.6 x 105 A/-, and the electric current Ll: was not applied to the kl film 5 (conventional method), and the current density of A7!11944 was set to the same value for the remaining 10 films. At the same time, a DC voltage of 30 V was applied to the A4 film 6 (method of the present invention), and the time required for failure (disconnection) to occur in the pattern Fl was measured.
第3図から明らかなように、Aj膜6に電圧を印加した
本発明の方法でに、試験試料が故障する時間が従来の方
法にくらべて大幅に短縮さハている。例メーば、竿数の
試別に故障が発生した時(故障60%)の試験時間は、
本発明の方法で約250時間、従来の方法で約400時
間であり、約150時間の時間短縮がはかられている。As is clear from FIG. 3, in the method of the present invention in which a voltage is applied to the Aj film 6, the time required for the test sample to fail is significantly reduced compared to the conventional method. For example, when a failure occurs during testing the number of rods (failure 60%), the test time is:
The method of the present invention takes about 250 hours, and the conventional method takes about 400 hours, which is a time reduction of about 150 hours.
脚、上説明したところから明らかなように、本発明のエ
レクトロマイクレージョンの加速試験方法は、実使用に
極めて近い条Pにでなされるとともに、試験時間を大幅
に短縮できるものであり、試験作業能率の飛躍的な向上
効果に加λ−で、配線膜評価の精度を大幅に高める効果
を奏する。As is clear from the above explanation, the accelerated test method for electromicrocation of the present invention can be performed in a condition P that is very close to that in actual use, and can significantly shorten the test time. In addition to the effect of dramatically improving work efficiency, λ- has the effect of greatly increasing the accuracy of wiring film evaluation.
なお、以上の説明では、試験試料として第1図で示すも
のを示したが、この例に限られるものではなく1例えば
、第4図で示すようにAl膜6がA71!膜4の直下に
実質的に平行に延びているもの、あるいは、第5図で示
すように、Al暎4と5が絶縁膜2の上に並設されてい
るもの、さらに、第1図、第4図の構成でA7J膜4と
5の上下関係を逆にしたものなどを用いてもよい。捷だ
、これらの試験試料に、最」二層として表面保護膜に相
当す二る絶縁膜を形成してもよい。In the above explanation, the test sample shown in FIG. 1 was shown, but the test sample is not limited to this example. For example, as shown in FIG. 4, the Al film 6 is A71! 5, the Al layers 4 and 5 are arranged in parallel on the insulating film 2, as shown in FIG. It is also possible to use the configuration shown in FIG. 4 with the A7J films 4 and 5 arranged in reverse order. Alternatively, two insulating films, which correspond to surface protective films, may be formed on these test samples as the second most layer.
第1図、第4図お」:び第6図は末完IJIのエレク験
方法を定性的に説11’lするだめの模式図、第3図は
本発明の効果を確認するための1に軟実験の結果を示す
図である。
1・・・・・・シリコン基板、2,3・・・・・・絶縁
膜、4゜6・・・・・・A/j膜、6・・・・・・電気
力線、7・・・・・・A6イオン流速。
代理人の氏名 弁理士 中 尾 敗 男 ほか1名第1
図Figure 1, Figure 4 and Figure 6 are schematic diagrams for qualitatively explaining the electric test method of IJI, and Figure 3 is a schematic diagram for confirming the effect of the present invention. FIG. 2 is a diagram showing the results of a soft experiment. 1... Silicon substrate, 2, 3... Insulating film, 4゜6... A/j film, 6... Lines of electric force, 7... ...A6 ion flow rate. Name of agent: Patent attorney Masao Nakao and 1 other person No. 1
figure
Claims (5)
第2金属配線膜を近接配置した試験試料の前記第1金属
配線膜に電流を流すとともに、前記第2金属配線膜に電
圧を印加するかもしくは電流を流し、この状態を保持す
ることを特徴とするエレクトロマイグレーションの加速
試験方法。(1) A current is passed through the first metal wiring film of a test sample in which a second metal wiring film is placed close to the first metal wiring film to be tested formed on the substrate, and the second metal wiring film is passed through the second metal wiring film. An accelerated electromigration test method characterized by applying a voltage or flowing a current and maintaining this state.
間に絶縁膜が配設されていることを特徴とする特許請求
の範囲第1項記載のエレクトロマイグレーションの加速
試験方法。(2) The electromigration accelerated testing method according to claim 1, wherein an insulating film is provided between the first metal wiring film and the second metal wiring film of the test sample.
体的に交差していることを特徴とする特許請求の範囲第
1項記載のエレクトロマイグレーションの加速試験方法
。(3) The electromigration accelerated testing method according to claim 1, wherein the first metal wiring film and the second metal wiring film of the test sample intersect three-dimensionally.
絶縁膜を挾んで平行にのびていることを特徴とする特許
請求の範囲第1項に記載のエレクトロマイグレーション
の加速試験方法。(4) The electromigration accelerated test method according to claim 1, wherein the first metal wiring film and the second metal wiring film of the test sample extend in parallel with an insulating film sandwiched therebetween.
一平面上に並設されている仁とを特徴とする特許請求の
範囲第1項記載のエレクトロマイグレーションの加速試
験方法。(5) The electromigration accelerated testing method according to claim 1, characterized in that the first metal wiring film and the second metal wiring film of the test sample are arranged side by side on the same plane.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56111853A JPS5814069A (en) | 1981-07-16 | 1981-07-16 | Acceleration test of electro-migration |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56111853A JPS5814069A (en) | 1981-07-16 | 1981-07-16 | Acceleration test of electro-migration |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5814069A true JPS5814069A (en) | 1983-01-26 |
JPH0124271B2 JPH0124271B2 (en) | 1989-05-10 |
Family
ID=14571792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56111853A Granted JPS5814069A (en) | 1981-07-16 | 1981-07-16 | Acceleration test of electro-migration |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5814069A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4652812A (en) * | 1984-11-27 | 1987-03-24 | Harris Corporation | One-sided ion migration velocity measurement and electromigration failure warning device |
USRE32625E (en) * | 1983-01-05 | 1988-03-15 | Syracuse University | Dynamic testing of electrical conductors |
US4739258A (en) * | 1986-07-11 | 1988-04-19 | Syracuse University | Dynamic testing of thin-film conductor |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04116561U (en) * | 1991-02-01 | 1992-10-19 | アラコ株式会社 | door lock device |
-
1981
- 1981-07-16 JP JP56111853A patent/JPS5814069A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE32625E (en) * | 1983-01-05 | 1988-03-15 | Syracuse University | Dynamic testing of electrical conductors |
US4652812A (en) * | 1984-11-27 | 1987-03-24 | Harris Corporation | One-sided ion migration velocity measurement and electromigration failure warning device |
US4739258A (en) * | 1986-07-11 | 1988-04-19 | Syracuse University | Dynamic testing of thin-film conductor |
Also Published As
Publication number | Publication date |
---|---|
JPH0124271B2 (en) | 1989-05-10 |
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