JPS58140132A - Manufacture of cz high resistance wafer - Google Patents
Manufacture of cz high resistance waferInfo
- Publication number
- JPS58140132A JPS58140132A JP2201782A JP2201782A JPS58140132A JP S58140132 A JPS58140132 A JP S58140132A JP 2201782 A JP2201782 A JP 2201782A JP 2201782 A JP2201782 A JP 2201782A JP S58140132 A JPS58140132 A JP S58140132A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- heat treatment
- resistance
- high resistance
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000011282 treatment Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000001186 cumulative effect Effects 0.000 claims 1
- 238000009827 uniform distribution Methods 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 25
- 238000009826 distribution Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- 230000000295 complement effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 210000003127 knee Anatomy 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体シリコンウェハの製造方法に関し、さ
らに詳しくは、高抵抗かつ均一な抵抗分布を目的とした
ウェハ製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor silicon wafer, and more particularly to a method for manufacturing a wafer aiming at high resistance and uniform resistance distribution.
最近のデバイスでは、高抵抗でしかも均一な抵抗分布ヲ
をする単結晶基板が要求されて来ている。Recent devices require single-crystal substrates with high resistance and uniform resistance distribution.
例えば高速ＲＡＭの場合５０〜１００Ω−１の基板が必
要である。シリコン単結晶の作り方にはフローティング
ゾーン法（ＦＺ法）と引上法（Ｃ２法）とがある。ＦＺ
法では、上記のような高抵抗単結晶の製作が容易である
が、ＦＺウェハを高速ＲＡＭの基板として使用した場合
、次の２つの問題点がある。For example, in the case of a high-speed RAM, a substrate of 50 to 100 Ω-1 is required. There are two ways to make silicon single crystals: the floating zone method (FZ method) and the pulling method (C2 method). FZ
With this method, it is easy to manufacture a high-resistance single crystal as described above, but when an FZ wafer is used as a substrate for a high-speed RAM, there are the following two problems.
■しきい値電圧（ｖｔｈ）の変動が大きい。特にエンハ
ンスメント形ＴｒにおいてはＦＺウエノ・の変動（σ）
はＣｚウエノ・０２倍近く大きい（第１Ａ図、第１Ｂ図
参照）。(2) Fluctuations in threshold voltage (vth) are large. Especially in the enhancement type Tr, the fluctuation (σ) of FZ
is nearly twice as large as Cz Ueno.02 (see Figures 1A and 1B).
■バルクの酸素の析出効果を利用するイントリンシック
・ゲッタリング（ＩＧ）には、１．５×１０１８ｆｆｉ
−３以上の格子間酸素濃度を必要とするが、Ｆ袷単結晶
Ｖ？−は２×１０１６ｆｆ−３以下の酸素しか含まれて
おらず、ウェハ内部に酸素を析出させることができず、
従って１０効果を利用することができない。■Intrinsic gettering (IG), which utilizes the precipitation effect of bulk oxygen, requires 1.5×1018ffi.
-3 or more interstitial oxygen concentration is required, but F-lined single crystal V? - contains only less than 2 x 1016ff-3 of oxygen, and oxygen cannot be deposited inside the wafer,
Therefore, the 10 effect cannot be used.
これに対してＣ２法では、ｖｔｈの変動が小さく、高温
熱処理を行ってＩＧ効果を利用することができるが、５
０Ω−１以上の高抵抗のウェハを効率よく安定的に作り
出すことが非常に難かしいという問題点があった。即ち
、結晶中の酸素は高温熱処理によりＩＧ効果をもたらす
一方、約４５０ ℃で長時間熱処理すると酸素ドナー（
サーマルドナーとも云われる）が発生し、高抵抗結晶で
はとくにこの影響が現われる。そしてこのサーマルドナ
ーは６５０℃で０．５〜１．０時間という短時間熱処理
すると消滅することがよく知られており、ウェハ加工上
行われている。しかし、抵抗値の分布は必ずしも均一に
することができず、６５０℃の熱処理をさらに続けても
サーマルドナーとは別のドナーと考えられるニュードナ
ーが形成され、より改善することができなかった。特に
ニュードナーによる抵抗値の変動は、Ｐ形単結晶におい
て発生しゃすい。On the other hand, in the C2 method, the variation in vth is small and the IG effect can be utilized by performing high temperature heat treatment.
There has been a problem in that it is very difficult to efficiently and stably produce wafers with a high resistance of 0Ω-1 or more. That is, while oxygen in the crystal produces an IG effect through high-temperature heat treatment, oxygen donor (
(also called a thermal donor) is generated, and this effect is particularly noticeable in high-resistance crystals. It is well known that this thermal donor disappears when heat treatment is performed at 650° C. for a short time of 0.5 to 1.0 hours, and this is done during wafer processing. However, the distribution of resistance values could not necessarily be made uniform, and even if the heat treatment at 650° C. was continued, a new donor, which was considered to be a donor different from the thermal donor, was formed, and further improvement could not be achieved. In particular, fluctuations in resistance due to new donors are likely to occur in P-type single crystals.
本発明の目的は、Ｖｔｈの変動が小さく、■Ｇ効果をも
つ引上法（ＣＺ法）により得られたＰ形単結晶から、高
抵抗でありがつウェハ面内で均一な比抵抗分布を有する
というｃｚ高抵抗ウェハの製造方法を提供することにあ
る。The purpose of the present invention is to obtain a high-resistance, uniform resistivity distribution within the wafer surface from a P-type single crystal obtained by the pulling method (CZ method) with small Vth fluctuations and a G effect. An object of the present invention is to provide a method for manufacturing a cz high resistance wafer.
本発明は、５５０〜９００ Ｃの温度範囲の熱処理にお
けるニュードナーの発生状況と、発生したニュードナー
の挙動についての知見を得、このニュードナーをＰ形ア
クセプタに相補させることによって有効に利用しようと
するものである。The present invention aims to gain knowledge of the state of new donor generation during heat treatment in the temperature range of 550 to 900 C and the behavior of the generated new donors, and to utilize these new donors effectively by complementing them with P-type acceptors. It is something to do.
第２図は、５５０〜９００Ｃの温度範囲の熱処理におけ
るニュードナーの発生状況を代表的に説明するために、
６５０℃における熱処理時間をパラメーターとしたとき
のニュードナーの発生状況を示したグラフである。そし
て試料として４種類の酸素濃度をもつウェハについて調
べた。FIG. 2 is a diagram for representatively explaining the state of new donor generation during heat treatment in the temperature range of 550 to 900C.
It is a graph showing the state of new donor generation when heat treatment time at 650° C. is used as a parameter. Wafers with four different oxygen concentrations were examined as samples.
先ず、ニュードナーの相補作用′によって高抵抗を安定
に保つために、ニュードナーの発生量が熱処理時間に対
して安定的な範囲をもつ単結晶の酸素濃度が決められた
。第２図に明らかなように、そのような酸素濃度は１．
５ｘ１０１８ｗ−”以上である。First, in order to keep the high resistance stable through the complementary action of new donors, the oxygen concentration of the single crystal was determined so that the amount of new donors generated was within a stable range with respect to the heat treatment time. As is evident in FIG. 2, such an oxygen concentration is 1.
5x1018w-" or more.
この酸素濃度は十分なＩＧ効果をもっている。また第２
図にみるように、単結晶の酸素濃度が高ければニュード
ナーの発生量が大きい。従って、ニュードナーの相補作
用によりＰ形の比較的低抵抗の単結晶からＰ形高抵抗ウ
ェハを得るためには、１．５×１０１８４−３以上の酸
素濃度の単結晶を用いるのが好適であり、また同じくＮ
形高抵抗ウェハを得るためには、１．７ Ｘ １０１８
〜１．８ＸＩＯ１８程度の酸素濃度の学結晶を用いるの
がよい。This oxygen concentration has a sufficient IG effect. Also the second
As shown in the figure, the higher the oxygen concentration in the single crystal, the greater the amount of new donors generated. Therefore, in order to obtain a P-type high-resistance wafer from a relatively low-resistance P-type single crystal through the complementary action of new donors, it is preferable to use a single crystal with an oxygen concentration of 1.5×10184-3 or more. Yes, also N
To obtain a shaped high resistance wafer, 1.7 x 1018
It is preferable to use a scientific crystal with an oxygen concentration of about 1.8XIO18.
次に、第２図にみるように、１．５ Ｘ １０１８α−
３以上の酸素濃度のウェハは、６５０℃の熱処理を３０
〜４０時間受けるとニュードナーが発生し、５０時間で
発生が・飽和することがわかる。同様に５５０〜９００
℃の熱処理をした場合には、２０〜４０時間でニュード
ナーが発生し、４０〜５０時間で飽和する。従って５５
０〜９００℃の熱処理によってニュードナーの発生を飽
和させ安定な相補作用を行わせるためには、３０時間を
超えた熱処理時間を与えればよい。Next, as shown in Figure 2, 1.5 x 1018α-
Wafers with an oxygen concentration of 3 or higher are heat treated at 650°C for 30 minutes.
It can be seen that new donors are generated after 40 hours of exposure, and the generation is saturated after 50 hours. Similarly 550-900
In the case of heat treatment at .degree. C., new donors are generated in 20 to 40 hours and saturated in 40 to 50 hours. Therefore 55
In order to saturate the generation of new donors and perform a stable complementary action by heat treatment at 0 to 900°C, it is sufficient to give the heat treatment for more than 30 hours.
この熱処理時間は２回以上の熱処理のスケジュールによ
ることもできる。This heat treatment time can also be based on a schedule of two or more heat treatments.
特に５５０〜．９００ ｔ？、の熱処理を５０時間以上
行った場合は、発生したニー−ドナーが極めて安定化し
、その後の低温又は高温の熱処理工程でも消滅すること
がない。しかしながら１００時間を超えるほどの長時間
熱処理をすると外部の汚染をとり込むこととなるので好
ましくない。Especially from 550. 900 tons? When the heat treatment is carried out for 50 hours or more, the generated knee donors become extremely stable and do not disappear even in the subsequent heat treatment process at low or high temperatures. However, if the heat treatment is carried out for a long time exceeding 100 hours, external contamination will be introduced, which is not preferable.
また、ニュードナーの発生は５５０〜９ｏｏ℃の熱処理
の前工程に、３５０〜５５０ ℃の前熱処理を２時間以
上行うと促進されることがわかった。このような前熱処
理はニュードナーの相補作用によりＮ形高抵抗ウェハを
作る場合に適用すると極めて容易にＰ形からＮ形に転換
することができる。Furthermore, it has been found that the generation of new donors is promoted by performing a preheat treatment at 350 to 550°C for 2 hours or more before the heat treatment at 550 to 90°C. When such pre-heat treatment is applied to the production of N-type high resistance wafers due to the complementary action of new donors, it is possible to convert the P-type to the N-type very easily.
以上のような知見に基づき、本発明は、引上法により得
られたＰ形シリフン単結晶からウェハに加工する工程に
おいて、該単結晶として格子間酸素濃度が１．５ Ｘ
Ｉ Ｑ１８ｃｍ−３以上のものを用い、該加工工程中に
温度範囲５５０〜９００ Ｃの熱処理を、少なくとも１
回かつ熱処理時間の累計が３０時間を超えた時間行うこ
とを特徴とする安定した高抵抗の半導体シリコンウェハ
の製造方法を提供するものである。Based on the above findings, the present invention provides a process for processing a P-type silicon single crystal obtained by a pulling method into a wafer, in which the single crystal has an interstitial oxygen concentration of 1.5
IQ of 18cm-3 or more is used, and heat treatment at a temperature range of 550 to 900 C is performed at least once during the processing process.
The present invention provides a method for manufacturing a semiconductor silicon wafer with stable high resistance, characterized in that the heat treatment is performed for a total of more than 30 hours.
Ｐ形高抵抗ウェハを得る第１実施例について説明する。 A first example of obtaining a P-type high resistance wafer will be described.
先ず、Ｃ２法で引上げたρ＝４２０−備。First, ρ=420-bi was raised using the C2 method.
ＣＯｉ ］ −１，５４ｘ １０１８ＣＩＩＩ−３のＰ
形単結晶を用意し、スライス及びラッピングを施してウ
ェハ形状に加工する。このものの拡がり抵抗法によるウ
ェハ面内の比抵抗分布を測定したところ、第６Ａ図に示
したよう（Ｃ，その分布は大きく△Ｒは５３チにも達し
ている。COi] -1,54x 1018CIII-3 P
A shaped single crystal is prepared and processed into a wafer shape by slicing and wrapping. When the resistivity distribution in the wafer plane of this product was measured by the spreading resistance method, as shown in FIG. 6A (C), the distribution was large and ΔR reached as much as 53 inches.
このウニハラ６５０℃で５０時間熱処理した。この熱処
理の過程で、サーマルドナーは通常１５〜３０分間でほ
ぼ消失し、２５〜４０時間の間でニュードナーが発生し
、４０〜５０時間で飽和に達し、ρ−１１３Ω−備とい
う元の抵抗の２．６倍の高抵抗で安定化する。そのウェ
ハ面内の比抵抗分布は、第６Ｂ図に示したように、ΔＲ
は４．８％と著しく改善することができた。この熱処理
をしたウェハはその後ケミカルポリッシング及び鏡面研
摩を施して半導体装置を製造したが、その過程の熱処理
によって安定した高抵抗性は変らなかった。This sea urchin crab was heat-treated at 650° C. for 50 hours. During this heat treatment process, thermal donors usually disappear in 15 to 30 minutes, new donors are generated in 25 to 40 hours, reach saturation in 40 to 50 hours, and return to the original resistance of ρ-113Ω-beta. Stabilizes with a resistance 2.6 times higher than that of The specific resistance distribution within the wafer plane is ΔR, as shown in FIG. 6B.
was able to be significantly improved to 4.8%. The heat-treated wafer was then subjected to chemical polishing and mirror polishing to manufacture semiconductor devices, but the stable high resistance remained unchanged due to the heat treatment during this process.
次にＮ形高抵抗ウェハを得る第２実施例について説明す
る。Ｃ２法で引上げたρ＝４１０−ｃ、〔Ｑｉ）−１，
７３Ｘ Ｉ Ｑ１８ｔＭ−３のＰ形単結晶を用意する。Next, a second example for obtaining an N-type high resistance wafer will be described. ρ raised by C2 method = 410-c, [Qi)-1,
A P-type single crystal of 73X I Q18tM-3 is prepared.
Ｐ形つェハからＮ形高抵抗ウェハにするためにニュード
ナーの発生を効果的にすることがよい。このため、５０
０℃で５時間前熱処理を行い、次いで６５０℃で７０時
間ニュードナー発生の熱処理を行ったところ、ニー−ド
ナーの発生によってＰ形はＮ形に転換し、Ｎ形でρ＝１
２２０−１という高抵抗値のウェハを得た。その面内比
抵抗分布は、第４Ａ図のΔＲ＝５２ ％のものが第４Ｂ
図のようにΔＲ＝４．４％と著しく改善させることがで
きた。In order to convert a P-type wafer into an N-type high-resistance wafer, it is preferable to effectively generate new donors. For this reason, 50
When pre-heat treatment was performed at 0°C for 5 hours, and then heat treatment was performed at 650°C for 70 hours to generate new donors, the P type was converted to the N type due to the generation of knee donors, and in the N type, ρ = 1.
A wafer with a high resistance value of 220-1 was obtained. The in-plane resistivity distribution of ΔR=52% in Figure 4A is the one in Figure 4B.
As shown in the figure, a significant improvement was achieved with ΔR=4.4%.
第１実施例、第２実施例のいずれのウエノ・においても
、Ｃ２法の特長である次の２点、即ちＶｔｈの変動が小
さいこととＩＣ効果のあることが認められた。In both the first example and the second example, the following two features of the C2 method were observed: small fluctuations in Vth and IC effect.
本発明によれば、酸素濃度１．５ Ｘ １０１８ｆｆｉ
−３以上の単結晶を用い温度範囲５５０〜９００ Ｃの
熱処理全３０時間以上という長時間行うことにｌよって
、ニュードナーが安定的に発生し、従ってＰ形又はＮ形
高抵抗つエノ・が従来方法と異なり容易にかつ面内の分
布が均一に、しかもｖｔｈの変動が小さく、有効なＩＣ
効果を伴って得ることができる。According to the invention, the oxygen concentration is 1.5 x 1018ffi
By performing heat treatment for a total of 30 hours or more at a temperature range of 550 to 900 C using a single crystal of −3 or higher, new donors are stably generated, and therefore P-type or N-type high-resistance nitrogen is generated. Unlike conventional methods, it is easy to create an effective IC with uniform in-plane distribution and small vth fluctuations.
can be obtained with effect.
第１Ａ図及び第１Ｂ図はＣ２法とＦｚ法のウェハのＶｔ
ｈの分布を説明するグラフ、第２図は本発明の６５０℃
熱処理時間とニュードナー発生量の関係を示すグラフ、
第６Ａ図及び第３Ｂ図は本発明のＰ形高抵抗つエノ・の
面内比抵抗分布の改善を示すグラフ、第４Ａ図及び第４
Ｂ図は、本発明のＮ形高抵抗つエノ・の面内比抵抗分布
の改善を示すグラフである。
特許出願人 東京芝浦電気株式会社
１６３Figures 1A and 1B show the Vt of the wafer for the C2 method and the Fz method.
Figure 2 is a graph explaining the distribution of h at 650°C according to the present invention.
Graph showing the relationship between heat treatment time and amount of new donors generated,
Figures 6A and 3B are graphs showing improvements in the in-plane resistivity distribution of the P-type high-resistance tube of the present invention, and Figures 4A and 4
Figure B is a graph showing improvement in the in-plane resistivity distribution of the N-type high resistance tube of the present invention. Patent applicant: Tokyo Shibaura Electric Co., Ltd. 163
Claims (1)
ハに加工する工程において、該単結晶として格子間酸素
濃度が１．５Ｘ１０ ［以上のもの管用い、該加工工程
中に温度範囲５５０〜９００℃の熱処理を、少なくとも
１回かつ熱処理時間の累計が３０時間を超えた時間行う
ことを特徴とする半導体シリコンウェハの製造方法。 ２ 温度範囲５５０〜９００Ｌの熱処理の前工程に、温
度範囲３５０〜５５０℃の前熱処理を、少なくとも１回
かつ前熱処理時間の累計が２時間以上の時間行う、特許
請求の範囲第１項記載の製造方法。 ６ 製造される半導体シリコンウェハが、Ｎ形シリコン
ウェハである、特許請求の範囲第１項記載の製造方法。[Claims] 1. In the step of processing a P-type silicon single crystal obtained by a pulling method into a wafer, the single crystal has an interstitial oxygen concentration of 1.5×10 [or more]. A method for manufacturing a semiconductor silicon wafer, comprising performing heat treatment at a temperature range of 550 to 900° C. at least once for a total heat treatment time of more than 30 hours. 2. The method according to claim 1, wherein preheat treatment at a temperature range of 350 to 550°C is performed at least once and for a cumulative preheat treatment time of 2 hours or more before the heat treatment at a temperature range of 550 to 900 L. Production method. 6. The manufacturing method according to claim 1, wherein the semiconductor silicon wafer to be manufactured is an N-type silicon wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201782A JPS58140132A (en) | 1982-02-16 | 1982-02-16 | Manufacture of cz high resistance wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201782A JPS58140132A (en) | 1982-02-16 | 1982-02-16 | Manufacture of cz high resistance wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58140132A true JPS58140132A (en) | 1983-08-19 |
Family
ID=12071214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2201782A Pending JPS58140132A (en) | 1982-02-16 | 1982-02-16 | Manufacture of cz high resistance wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58140132A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102167A (en) * | 1991-10-07 | 1993-04-23 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon |
| JP2016500641A (en) * | 2012-10-23 | 2016-01-14 | コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブＣｏｍｍｉｓｓａｒｉａｔ Ａｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓａｌｔｅｒｎａｔｉｖｅｓ | Method for forming a doped silicon ingot with uniform resistance |
-
1982
- 1982-02-16 JP JP2201782A patent/JPS58140132A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102167A (en) * | 1991-10-07 | 1993-04-23 | Shin Etsu Handotai Co Ltd | Heat treatment of silicon |
| JP2016500641A (en) * | 2012-10-23 | 2016-01-14 | コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブＣｏｍｍｉｓｓａｒｉａｔ Ａｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓａｌｔｅｒｎａｔｉｖｅｓ | Method for forming a doped silicon ingot with uniform resistance |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0231493B2 (en) | ||
| JPS583375B2 (en) | Manufacturing method of silicon single crystal wafer | |
| JP2007176725A (en) | Method for manufacturing neutron-irradiated silicon single crystal | |
| Patrick et al. | The effect of SiO2 precipitation in Si on generation currents in MOS capacitors | |
| JPH0787187B2 (en) | Method for manufacturing GaAs compound semiconductor substrate | |
| JPS58140132A (en) | Manufacture of cz high resistance wafer | |
| JPH0891993A (en) | Production of silicon single crystal substrate and method for quality control | |
| JPH0523494B2 (en) | ||
| JPH04233219A (en) | Manufacture of products comprising semiconductor devices | |
| Peter et al. | Prolonged and rapid thermal annealing of boron implanted silicon | |
| Rai‐Choudhury | Substrate Surface Preparation and Its Effect on Epitaxial Silicon | |
| EP3675155A1 (en) | Recombination lifetime control method | |
| JP2001077120A (en) | Manufacture of epitaxial silicon wafer | |
| JP2742856B2 (en) | Semiconductor thin film manufacturing method | |
| KR102104074B1 (en) | Method for manufacturing silicon wafer | |
| JPH11288942A (en) | Manufacture of semiconductor device | |
| Borsch et al. | Photoelectrical properties of CdxHg1-xTe epitaxial layers irradiated by nanosecond laser pulses | |
| JPS5650520A (en) | Processing method of semiconductor substrate | |
| US3175975A (en) | Heat treatment of iii-v compound semiconductors | |
| Londos et al. | Production and evolution of defects in neutron-irradiated Si subjected to thermal pre-treatments under hydrostatic pressure | |
| Kissinger et al. | Verification of a method to detect grown-in oxide precipitate nuclei in Czochralski silicon | |
| Hardeman et al. | Oxide removal from silicon wafers studied by transient mass spectrometry and X-ray photoelectron spectroscopy | |
| JPS62139335A (en) | Surface cleaning process | |
| Kawasumi et al. | Novel optical features in Cd+ ion-implanted LEC-grown GaAs | |
| Wagner | TEM Observations of Defects in Ge‐Doped LPE GaAs and Al0. 4Ga0. 6As |