JPS58138102U - sequence controller - Google Patents
sequence controllerInfo
- Publication number
- JPS58138102U JPS58138102U JP3566982U JP3566982U JPS58138102U JP S58138102 U JPS58138102 U JP S58138102U JP 3566982 U JP3566982 U JP 3566982U JP 3566982 U JP3566982 U JP 3566982U JP S58138102 U JPS58138102 U JP S58138102U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- external memory
- sequence controller
- lower case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例のシーケンスコントローラのブ
ロック図、第２図は同上の全体の斜視図、第３図は同上
のシーケンサ本体の分解斜視図、第４図は同上の断面図
である。
１は外部メモリユニット、２は入出力インターフェイス
、３はシーケンサ本体、５は下ケース、６は第１のプリ
ント基板、７は第２のプリント基板、８は上ケース、９
は演算制御部、１３ａ。
１３ｂは段部、１７は接続コネクタ、１８ａ。
１８ｂは被接続コネクタを示す。Fig. 1 is a block diagram of a sequence controller according to an embodiment of the present invention, Fig. 2 is an overall perspective view of the same, Fig. 3 is an exploded perspective view of the sequencer main body of the above, and Fig. 4 is a sectional view of the same. . 1 is an external memory unit, 2 is an input/output interface, 3 is a sequencer main body, 5 is a lower case, 6 is a first printed circuit board, 7 is a second printed circuit board, 8 is an upper case, 9
is an arithmetic control section, 13a. 13b is a stepped portion, 17 is a connecting connector, and 18a. 18b indicates a connector to be connected.
Claims (1)
が書き込まれた外部メモリユニットを、この外部メモリ
ユニットのシーケンスプログラムを実行して入出力イン
ターフェイスを介して負荷を制御する演算制御部を有す
るシーケンサ本体に着脱自在に装着したシーケンスコン
トローラにおいて、シーケンサ本体の上面が開口した下
ケース内に演算制御部等の電子回路を実装した第１のプ
リント基板を装着し、下面が開口して下ケースの上面開
口部を覆設嵌合する上ケース内に入出力インターフェイ
スの電子回路を実装した第２のプリント基板を第１のプ
リント基板と平行に対面配置し、上ケースと下ケースと
の開口側端部に嵌合用段部を夫々形成し、第２のプリン
ト基板の上ケースの内側面近傍の端部の上下面より接続
コネクタを夫々突設し、この接続コネクタに対応する位
置の第１のプリント基板の上面と外部メモリユニットの
下面とに夫々被接続コネクタを設けて成ることを特徴と
するシーケンスコントローラ。An external memory unit in which a sequence program for sequentially controlling the load is written can be detachably attached to the sequencer body, which has an arithmetic control section that executes the sequence program of this external memory unit and controls the load via an input/output interface. In the installed sequence controller, the first printed circuit board on which electronic circuits such as arithmetic control units are mounted is installed in the lower case, which has an open top surface of the sequencer main body, and the bottom surface is open and covers the top surface opening of the lower case. A second printed circuit board on which an electronic circuit for an input/output interface is mounted is placed in the upper case to be mated, parallel to and facing the first printed circuit board, and a mating step is provided at the opening side end of the upper case and the lower case. connecting connectors are provided respectively protruding from the upper and lower surfaces of the ends near the inner surface of the upper case of the second printed circuit board, and the upper surface of the first printed circuit board and external memory are formed at positions corresponding to the connecting connectors. A sequence controller characterized in that a connector is provided on the bottom surface of the unit and a connector to be connected to the bottom surface of the unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3566982U JPS58138102U (en) | 1982-03-13 | 1982-03-13 | sequence controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3566982U JPS58138102U (en) | 1982-03-13 | 1982-03-13 | sequence controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58138102U true JPS58138102U (en) | 1983-09-17 |
| JPS6243363Y2 JPS6243363Y2 (en) | 1987-11-11 |
Family
ID=30047130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3566982U Granted JPS58138102U (en) | 1982-03-13 | 1982-03-13 | sequence controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58138102U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012226631A (en) * | 2011-04-21 | 2012-11-15 | Mitsubishi Electric Corp | Unit type programmable controller |
-
1982
- 1982-03-13 JP JP3566982U patent/JPS58138102U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012226631A (en) * | 2011-04-21 | 2012-11-15 | Mitsubishi Electric Corp | Unit type programmable controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6243363Y2 (en) | 1987-11-11 |
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