JPS58137179A - Delaying device of digital signal - Google Patents

Abstract

PURPOSE:To simplify the hardware and to facilitate an easy change of delay time, etc. during the real time processing, by using a single signal delaying memory to form plural digital signal delaying lines. CONSTITUTION:A digital signal delaying device is provided with a current address storage part 3C which stores the read/write address to a digital signal delaying memory 1, an address control memory 3 consisting of storage parts 3T and 3B of upper limit/lower limit addresses of the memory 1, an adder circuit 21 which increases the current address value, a comparator 22 that compares the result of addition of the circuit 21 with the upper limit address given from the memory 3, and a multiplexer 23 which selects the result of addition or the lower limit address of the memory 3 based on the result of comparison of the comparator 22. Then the result of this selection is written to the storage part 3C.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal delay device for delaying a digitally converted audio signal, image signal, etc. using a digital signal delay memory, and in particular, the present invention relates to a digital signal delay device for delaying a digitally converted audio signal, image signal, etc. using a memory for digital signal delay. This invention relates to a digital signal delay circuit.

Generally, when processing digital signals such as digitally converted audio signals and video signals in real time, processing such as high-speed product-sum calculations and time delays is required. Currently, as a circuit configuration (/1-ware configuration) for performing digital signal delay processing, one that uses a multi-stage shift register is generally known, and the number of stages of this shift register and sampling The delay time is determined by the product of the period (the period of the shift clock).

However, when executing the above-mentioned real-time processing using a digital signal delay circuit using such a shift register, for example, if you want to change the delay time during processing, you have to change the number of stages of the shift register, which is not easy to change. isn't it. Furthermore, as shown in FIG. 1, for example, when a reverberation adding device or the like is configured using a plurality of delay circuits DL, the hardware structure becomes complicated. In particular, when trying to dynamically change the delay time of each delay circuit (DL) in a device like the one shown in FIG. 1, it is almost impossible with a delay circuit configuration using shift registers.
It is also uneconomical to use a large number of shift registers.

The present invention eliminates these conventional drawbacks, makes it possible to realize multiple signal delay lines with a relatively simple hardware configuration, and allows the number of delay lines and delay time to be arbitrarily set using software. An object of the present invention is to provide a digital signal delay device that can easily change delay time, etc. during real-time processing such as processing.

That is, the features of the digital signal delay device according to the present invention include a memo 1) for digital signal delay, a current address storage section for storing read and write addresses for this memory, and upper and lower limit addresses of the memory. An address management memory consisting of a storage section for storing each, an addition circuit for increasing the current address value from this address management memory, and an addition result from this addition circuit and the signal delay memory from the address management memory. A comparison circuit for comparing the upper limit address with the upper limit address, and a selection for selecting either the addition result from the addition circuit or the signal delay memory lower limit address from the address management memory according to the comparison result from this comparison circuit. circuit, and the selection result from this selection circuit is written into the current address storage section of the address management memory.

Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block circuit diagram showing one embodiment of the present invention. In FIG. 2, a memory block l (Signal Delay Memory, hereinafter referred to as SDM) for digital signal delay that can store, for example, l words of 24-bit digital signals in, for example, 64 words (65,536 words) has an address management unit 2 ( Add
ress Management Unit, hereinafter referred to as A
It's called MU. ), each word is accessed by a 16-bit memory address MA, for example.

Here, as the digital signal written to and read from the SDM 1 via the data bus DB, for example, a PCM audio signal, a digital video signal, etc. are used. In this case, the number of quantized bits of the PCM audio signal, etc. is about 14 or 16 bits, but considering the overflow during arithmetic processing such as multiplication of coefficients, the number of quantized bits handled by the digital signal processing system is The signal has a structure of 24 bits per word.

8DM1, for example, as shown in FIG. 3, has a total of 64 memory cells Ct + C2+ .
It is divided into n parts and used. These 1st to n1th
The boundary addresses (top address TA and bottom address BA) of the first memory cells C1, , Cn, and the address being accessed (current address CA) of each cell are
), the address management memory 3 (Add
Ress Management Memory,
Hereinafter referred to as AMM. ) is provided in the AMUZ. Each memory cell C, . The addresses may be discontinuous as in the second cell C2. ARM3 includes each memory cell C1-,,c,
4, the bottom address is the minimum value (lower limit value) of the address.
ss) Top address (Top Addr) which is the maximum value (upper limit value) of area 3B and 7 addresses that store B A.
It consists of three parts: an area 3T1 for storing TA and an area 3C for storing a current address CA between BA and TA as a value to be accessed.

When writing (initializing or changing) each of these addresses BA, TA, and CA, the host computer system 5 sends, for example, a 6-bit cell number designator for designating the number of the memory cell mentioned above, and each of the above addresses. 16-bit address data indicating addresses BA, TA, and CA are output, cell number designation data is sent to the AMU 2 via a multiplexer 6 as a switching selection means, and address data is sent to the AMU 2 via an address register 7, etc. being sent.

Here, in the internal circuit configuration of AMU2, adder circuit 2
1 is for adding (incrementing) 11I to the current address CA read from the area 3C of the AMM 3, and the addition result from the addition circuit 21, that is, the incremented current address data, is sent to the comparison circuit 22. , and multiplexer 23, respectively. The comparison circuit 22 compares the addition result with the top address TA read from the area 3T of the AMM 3, and sends the comparison result to the multiplexer 23.
to the switching control terminal. The multiplexer 23 has λMM
The bottom address BA from the area 3B of No. 3 and the addition result from the adder circuit 21 are switched and outputted according to the comparison result, and the top address TA
When the above addition result is greater than the above bottom address B
A is selected, and in other cases, the above addition result is selected and output. The output address from this multiplexer 23 is sent to the area 3C of the AMM 3 via the step 9 C% multiplexer 24, and is sent to the area 3C of the AMM 3, and
It is written in response to a write command WT from. That is, the current address CA in the area 3C is incremented by .degree. 1" every time a write command WT to the SDMI by the microprogram is output, and after reaching the top address TA, it is incremented again from the bottom address BA.

Next, the microcontroller program memory 11 shown in FIG. 2 is for configuring a signal delay line using the SDM1 in software by controlling such AMU2, and each microcontroller program The instructions are read out sequentially by a sequence 12 (also called a program counter). The microprogram memory 11 and sequencer 12 are
For example, a digital signal processing unit may be configured together with an ALU (logical operation unit), a multiplier, a register, etc. (not shown) that sends and receives signals to and from the data bus DB of the 24-bit digital signal. The sequencer 12, depending on the contents of the microinstruction and the state of the condition flag (or status flag),
Specifies the address of the microprogram memory 11 where the microinstruction to be executed next is stored. A microinstruction is usually expressed by several tens of bits per word, and is divided into several fields, such as a direct data field, a field that controls the ALU (logical operation unit), and a field that controls the sequencer 12. is provided. Furthermore, in the case of the present invention, the above SDM
A field for controlling the AMU 2 is provided for managing the AMU 1. Here, if the number of memory cells in SDM1 is up to 64, 6 bits are required to specify the cell number, and 2 bits are required to control reading and writing of SDM1. Therefore, a total of 8 bits of AMU control field (or S
DM control field). This AMU control feed address A is determined.

By the way, when using, for example, the first memory cell C1 in SDM1 as a delay line, the memory cell C1
The above bottom address i3A, which is the boundary address of 2,
) Tube addresses T A, and these addresses BA
, ~TA1, the current address CAL is A
It is necessary to write the cell number designation address of each area 3B, 3T, and 3C in the MMS in each word of rxJ in advance, that is, so-called initial setting. In this initial setting operation, the multiplexer 6 in the MCUJ is switched to the host computer system 5 side during the initial setting, and the host computer system 5 sends a signal specifying the cell number rlJ to each of the addresses BA s , TA + , and Each address data of CAi is sequentially sent to AMU2. In this case, each address B
When sequentially sending AD, TAt, and CAI, an address identification code for identifying them is sent at the same time.
Write to each of the above areas 3B, 3T1 and 3C.

After such initial settings have been made for all the memory cells to be used, the multiplexer 6 is switched to the microprogram memory 11 side, and the AMU 2 is microprogram controlled.

In this case, first, 0 is written to all words of SDM1 to perform a so-called all clear, and then the process moves to a digital signal delay processing loop. Within this processing loop,
SD accessed by the above current address CA
Read and write processing for the word of MI and increment processing for the address CA are performed.
On the microprogram, it is only necessary to specify the memory cell number and give read and write commands, and operations such as incrementing the current address CA and switching to the bottom address BA after reaching the top address TA are performed in 1. , is automatically performed inside the LMU2.

By the way, when specifying the cell number of SDM1 in the digital signal delay processing loop of the microprogram,
The current address CA of the word corresponding to the cell number of AMM3 is read, and the SDM
l is accessed.

If the access time of SDMi is about one microprogram instruction cycle or less, if the content data of the word accessed by the next microinstruction is input/output, the digital signal readout to SDMi,
Can write. In this case, in read mode,
Inside AMU2, the current address CA is not updated, and the SD address is
The data read from M1 may be sent via the data bus DB to a circuit unit that performs register, output, and gray processing (for example, a multiplier or a D/A converter. Also, in the write mode, the above-mentioned memory A write pulse is output in response to the next microinstruction after access, and this write pulse causes the digital data on the data bus DB to be
Write to the accessed word of DMl and write A
The current address CA is updated within the MU2, that is, the address data from the multiplexer 23 is taken in.

The operation timings in these read and write modes will be explained with reference to FIG. In FIG. 5, time T indicates one instruction cycle of the microprogram, the above-mentioned cell number designation is performed in conjunction with a read and write command between times 11 and 12, and SDM1 and data bus DB are connected between times 12 and 13. Data is exchanged between the two. In this case, when the cell number is designated at time t1, the current address storage area 3 of 8MM3
The current address CA read from C is determined at time '11 after a predetermined access time has elapsed, and from time t12 immediately after this time Ill, an address strobe pulse for SDMI is generated and access to SDM1 is performed. SDML can be read and written after an address access time determined by the characteristics of the memory device used, such as dynamic R
In the case of AM (Random Access Memory), the access time is about 100-odd nanoseconds. Then, the next instruction cycle, time t2. A write and read pulse is output at time 'ta just before the end of interval t3 (immediately before time t3), and the accessed word and data bus D are output.
Digital signal data is exchanged with B.

Here, between the time tit when the current address CA is determined and the pulse output time '13, inside the AMU 2, the addition port w121 increments the address CA, and the comparison circuit 22 increments the top address TA.
The multiplexer 23 performs a comparison with the address and selects the address from the multiplexer 23.
That is, the next address NA to access SDM1 in the next signal delay processing loop is sent to the current address storage area 3C via the multiplexer 24. Then, only at the write pulse output time t1m in the write operation mode, the next address NA
is written into the current address storage area 3C. Therefore, in one cycle of the signal delay processing loop by the microprogram, a digital signal is first written to the same word of 8DM1 that was JQI accessed by the current address CA during reading, and only then is the current address storage area 3C of AMM3 The current address CA is rewritten to the next address NA. The word written with this digital signal is then read out after all words of the memory cell used as a delay line (for example, the first memory cell C1) have been accessed. The delay time is the product of the total number of words in the memory cell, that is, the difference between the top address TA and the bottom address BA, and the time required for one cycle of the signal delay processing loop of the microprogram. In this case, by inserting a program in the signal delay processing loop that determines whether or not the sampling processing in the A/D converter has been completed, and repeats the check until the sampling processing is completed, the signal delay processing loop can be The time of one cycle of can be made to match the sampling period.

Here, for example, if the sampling clock frequency is 50
kHz (sampling period is 20μ1lIle), and the total number of words of the memory cell used as a delay line is 1.
In the case of 000 words, a delay time of 20m5c is obtained. Each time the number of words in the memory cell increases by one word, the delay time increases by 20μ (8), and conversely, each time the number of words decreases by one word, the delay time decreases by 20μ. The number of words can be easily increased or decreased by rewriting at least one of the bottom address BA and top address TA of the memory cell under control from the host computer.

Next, an example of a processing procedure when such a signal delay processing operation is performed by a microprogram is shown in the flowchart of FIG. In FIG. 6, before entering the signal delay processing loop as described above, the SDM
A so-called all-clear or initial reset operation is performed by writing "0°" into all words of l. After this step 31, a signal delay processing loop program is provided, and the top of this loop program A condition judgment step 32 is provided to check whether the A/D conversion has been completed.Every time sampling is performed in the A/D converter, the next step 3 is performed.
The operation of reading and writing digital signals to SDM1 from 3 onwards is performed centrally, and inside AMU2, A
The current address CA in the current address storage area 3C of M M 3 is automatically rewritten. First, step 33 is a step of storing A/D converted digital signal data in, for example, register Ra via the data bus DB. Next, steps 34 and 35 correspond to the operation of specifying a memory cell number to SDM1 and reading out digital signal data. That is, in step 34, for example, the first memory cell C
By sending a command to read 1 to AMU2, AMU
2 outputs the current address CA corresponding to the first memory cell, and accesses SDMl by using this address (l as the SDMI read address.
After an access time determined by the characteristics of the memory element used, the output data is determined and can be read.

For example, when a dynamic RAM is used as the SDM1, the output is generally determined after several hundred n5ecs.

When the output is determined, step 35 causes the output to appear on the data bus DB from SDM1. Data is stored in register Rh, for example. That is, it is possible to read 8DM1 with two microinstruction steps. Note that if the time to execute one step of a microinstruction (instruction cycle) is long, or if the access time of AMM3 and SDMl is sufficiently short, it is also possible to read out SDMl with a one-step microinstruction.

Next, step 36 is a write command for the first cell of SDMl, but at this point, by instructing AMU2 to write and specifying the cell number, the current corresponding to the first cell is Address CA is read and SDM1 is accessed. And S.D.
The write signal for Ml is output in the next step 37, and at this time, when the contents of register Ra storing the data from A/D converter 15 are placed on data bus DB, this value is written to 8BM1.

Next, the data read from the memory cell number of SDMl stored in the register Rb is sent to the D/A converter as in step 38, and then the process returns to the condition determination step 32. , a basic signal delay line can be constructed.

By the way, regarding the above-mentioned reverberation adding device, etc., which is configured using a plurality of signal delay lines, other memory cells are designated and read and written to the positions such as step 39 shown by the broken line in FIG. You can insert a program that causes the data to be delayed, or multiply the data read from each memory cell of the SDM1 by a coefficient to obtain the data before the delay (for example, A
/D converted data stored in the register Ra, etc.) by adding a program to add the data, etc.
This can be easily realized without any hardware changes. Also, from the host computer system 5 side, for example, during the waiting time for the end of A/D conversion in step 31, the memory cell number is specified and the bottom address BA or top address TAJ- is rewritten, and the signal delay line corresponding to each cell is The delay time can be changed dynamically.

As is clear from the above explanation, it is possible to realize the configuration of multiple digital signal delay lines using one SDMl, so independent hardware is not required for each delay line as in the case of using a shift register. The hardware can be simplified. In addition, the actual address management of SDMl is performed by AMU2, and this AMU
Since the read and write addresses (current addresses) are incremented within 2, the ALU etc. can perform other tasks during this time, and the throughput of the digital signal delay device as a whole can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a reverberation adding device configured using a plurality of digital signal delay lines, and FIG. 2 is a block circuit diagram showing an embodiment of the digital signal delay device according to the present invention. Figure 3 shows the signal delay memo IJsDM.
FIG. 4 is a diagram for explaining the structure of the address management memory, FIG. 5 is a timing chart showing the timing of each signal when executing microprogram read and write commands, and FIG. is a flowchart showing an example of a signal delay processing program. 1...SDM (signal delay memory) 2.
t...AMU (address management unit) 3.
・・・・・・・・・A44M (address management memory) 3B
...Bottom address storage area 3T...
Top address storage area 3C... Current address storage area 5... Host computer system 11... Micro program memory 2
1... Addition circuit 22... Comparison circuit 23... Multiplexer patent applicant Sony Corporation representative Patent attorney Kodo Koike 1) Sakae Mura - Matter 5m No. 61

Claims (1)

[Claims] An address management memory consisting of a memory for digital signal delay, a current address storage section for storing read and write addresses for this memory, and a storage section for storing the upper and lower limit addresses of the memory, respectively, and this address management memory. an addition circuit for increasing the current address value from the memory; a comparison circuit for comparing the addition result from the addition circuit with the upper limit address of the signal delay memory from the address management memory; and this comparison circuit. and a selection circuit that selects either the addition result from the addition circuit or the lower limit address of the signal delay memory from the address management memory according to the comparison result from the selection circuit. A digital signal delay device characterized in that the digital signal delay device is configured to write in a current address storage section of the address management memory.