JPS58137064A - Address extension system - Google Patents

Abstract

PURPOSE:To access physical address of a memory continuously, by splitting a main storage device into a plural segment blocks having a common section and a page number and applying a required processing for the designating part of a logical address. CONSTITUTION:A main storage device 6 is split into a plural segments SB having a prescribed size and a common section CB, and each SB is added with a page value. A logical address is outputted from a mu processor 4 via an address bus and data having a minimum m-bit number required for the expression of a page is outputted via a data bus. When a logical address designates the address of the CB in an address extension circuit 5, it is taken as the physical address of the memory 6 as it is and when the SB is indicated, m-bit is added to the upper- order of minimum n-bit required for the designation of the address of each SB area to form the physical address of the memory 6. Thus, when the memory is extended, since the capacity of memory extension is not changed depending on the size of the SB area, the physical address of the memory is accessed continuously without notifying the size of the SB.

Description

Detailed Description of the Invention (1) ゛Technical Field of the Invention The present invention relates to the use of segment blocks (
The present invention relates to an address expansion method that allows continuous access to physical addresses of the main storage device regardless of the size of the area (hereinafter abbreviated as 8B).

Φ) Technical Background Since the microcomputer has a 16-bit address bus, the main memory has a maximum of 64 words. However, with the demand for higher processing power, there are cases where the main storage device (hereinafter referred to as memory) requires more than 64 words.

(C) Prior art and problems Figure 1 shows the contents of physical addresses in the conventional address extension method, and Figure 2 shows the correspondence between logical addresses and physical addresses in the case of memory address specification. ,
■ indicates a physical address.

In the figure, 1 is an extended memory address designation area, 2 is a logical address area, and 3 is an area for determining whether an address is within a common block (hereinafter abbreviated as OB) or SB.

When expanding the memory, the microcontroller divides the logical address specifying the memory address into OB and 8B, as shown in Figure 21, and determines whether the upper bit in the 16-bit logical address area z in Figure 1 is OB or 8B. In order to judge whether it is 8B from OB based on the code in area 3, and to switch between multiple 8Bs if it is within SB, an 8B page ( 8B1, 882.- with page numbers.

) A designation code is inserted in 64 as the physical address of the memory so that a memory address larger than a word can be designated. However, in this case, "I bl" in Figure 2 (c)
' As shown in I..., an area equal to the OB area is omitted as a physical address. Therefore, if the size of the 8B area is reduced, the expandable memory capacity will be reduced.

(d) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks and to provide an address expansion method that allows continuous access to physical addresses of a memory regardless of the size of the SB area.

(e) Structure of the Invention In order to achieve the above object, the present invention divides a main storage device into a common section and a plurality of segment blocks of a predetermined size, and assigns a page value to each segment block. The address expansion means outputs a logical address via the address bus, and outputs m-bit data, which is the minimum number of bits necessary to represent the page value, via the data bus. If specified, it will be used as the primary address of the main memory, and if a segment block is specified, the address of each segment block area will be specified in the upper order of the required minimum number of bits n bits. This is an address extension method characterized by adding m bits to form the physical address of the main storage device.

(f) Embodiment of the Invention Below, an embodiment of the invention in which the memory is 1 megaword will be explained with reference to the drawings. Figure 3 is a conceptual diagram of the present invention, M41a is a diagram of the 20-bit physical address of the embodiment of the present invention, Figure 5 is a conceptual diagram of the expansion mechanism of the embodiment of the present invention, and Figure 6 is the implementation of the present invention. The circuit diagrams of the example address expansion circuit, Figures 7, 8, and 9 are the corresponding diagrams of the logical address (when 8B is word 32, word 16, and word 8) and physical address ■. It is.

In the figure, 4 is a microprocessor (hereinafter referred to as μ processor), 5 is an address expansion circuit, 6 is a 1M word memory, 7, 8, 9.17-1.17-2゜17-3.19
-1 to 19-7.21-1 to 21-3 are AND circuits, 1
0.18-1.1872.20-1 Ya 20-3 is an OR circuit, 16-1 to 16-3 are NOT circuits, 11 is a page register reading section, 12 is an 80I-di register writing section, 13 ~15 is a setting cap according to the size of the 8B area, and 13 is 1 when the word is 32.
4 is shorted to 16 when it is a word, and 15 is shorted to 8 when it is a word. R8-R3 are resistors.

In FIG. 3, word 7 is stored in logical address space 64 accessed by processor 4 using a 16-bit address.
As shown in (a) of Figures to Figure 9, depending on the size of each 8B area, OB is a word in 32, and 8B is a word in 32.
4Km-word in 32 of the word, OB in 48, word SB in 48, word in 64, word in 16 of word, OB in 56, 8B divided into words from 56 to 64, and the logical address is in OB. If the logical address is in the SB, it becomes a physical address that directly specifies the memory address, and if the logical address is in the SB, a 20-bit physical address is created from the page value and the logical address, as shown in FIG. This means that if the 0 position at the upper 0.1°2 position of the 16-bit logical address shown in FIG. 5 is between word 32 and word 64, it will be 11", and
Between words 2 and 64, the positions of 0 and 1 are @
1.11, and between the word 56 and the word 64, the position of 0°1.2 becomes "1, 1, 1". Therefore, depending on the size of the set SB area, this 0.1°2
By looking at the sign of the position, it can be determined whether this logical address indicates the inside of the OB area or the SB area. Here, if we assume that 8 and words are one page as the page value, as shown in Figures 7 to 9 (5) ■ (when 8B is 32 words, 8B1 is 4 pages, 8B2 is 8 pages, 8B30 is 12
4 pages and when 8B is 16 words, 8B1 is 6 pages 8B2 is 8 pages, 8B60 is 126 pages, when SB is 8 and words, 8B1 is 7 pages 8B2 is 8 pages 8
By setting B12G to 127 pages and specifying the page and address within the page, the address of 1 megaword memory can be specified. To specify this page value, if 8B of the 7 bits of the page value in Figure 5 is 32 words, then
Since the page value is skipped by 4 pages, it can be specified using the upper 5 bits, and when 8B is 16 words, the page value is skipped by 2 pages, so it can be specified using the upper 6 bits, and SB is 8.
When it is a word, it is continuous in units of one page, so 7 bits are required. - It takes 15 bits to specify the address of a word in 32, 14 bits to specify the address of a word in 16, and 13 bits to specify the address of a word in 8. Bye. Therefore, to specify a physical address within the 8B area, out of 20 bits, S
If B is 32 words, use the upper 5 bits as the page value index, and use the following 15 bits to specify the address within each 8B. If 8B is 16 words, use the page value specification. The upper 6 bits should be used, and the following 14 bits should be used to specify the address within each SB. Also, when 8B is a word, the upper 7 bits should be used to specify the page value, and the following 13 bits should be used to specify the address within each SB. It is sufficient to specify an address within each 8B. In this way, a 20-bit physical address is created. Therefore, by switching the page value, the physical address of one megaword of memory can be freely accessed.

The address expansion circuit shown in FIG. 6, which is a circuit for realizing the above, will be explained. The upper three bits ADO to AD2 of the 16-bit logical address ADO to ADZ5 from the μ processor 4 in FIG. 3 are AND circuits 21-1 to 21-. 3 and 17-1 to 17-34. Also S
The setting terminals 13, 14, and 15 are short-circuited according to the word B area 32, word 16, and four words 8. As a result, when the SB area 32 is a word, when the logical addressm DO is 0, the address is specified in the OB area, so the logical addresses ADO to AD15 become the physical addresses AOO to A15 of the memory.・When it is 1, it is 8B.
Since it is within the area, if you specify a page value of 8B using the upper 5 bits DO9 to D1B of the 7-bit data DO9 to D15 from the μ processor 4 and input it to the page register 12, this will specify the page value of 8B. The physical addresses BAOO to BAO3 and AOO are added to the upper half of the logical address ADZ-AD15 which specifies an address within 8B, resulting in 20 bits, and the physical address of the SB of the memory can be freely specified. When 8B is 16th word or 8th word, logical address ADO, ADI or ADO.

If ADI and AD2 are @1,1'' or @1,1,1'', it is within the SB area; otherwise, it is within the OB area. If it is within the OB area, the logical address becomes the actual physical address, just like the queen. If it is within the 8B area, specify the 8B page value using the upper 6 or 7 bits of the 7-bit data D09 to D15 from the μ processor 4 and input it to the page register 12, and this output will be the physical address AO2 to D15. Placed above A15 or AO3-A15 2
This becomes a 0-bit physical address, and you can freely specify the physical address of the SB in the memory. Visit page register 11゜12
is managed by software and has read or write codes RDPAG and W so that it can be saved in the event of an interrupt, etc.
It is possible to write the total on TPAG.

As described above, by inputting the 16-bit logical address specifying the address of the memory from the address bus of the μ processor 4 and the data specifying the page value of SB from the data bus to the address expansion circuit 5, the necessary portion can be 2 in total
This is a physical address that specifies a 0-bit memory address, and the physical address space of 1 megaword memory 6 can be freely accessed. The above example uses an address expansion circuit, but the 10th example uses an address expansion circuit.
The case of address extension using a program will be explained with reference to FIGS. In the case of FIG. 10, an address expansion graph is stored in the area 6m of the main memory 6, and the address is expanded according to the chart 70 in FIG. In other words! By Iku4 processor 4,
The address extension program is read from the area 6m of the memory 6.

Then, it is determined whether the logical address is in section 08 or section 8B. If it is in section 08, the logical address is output to address bus B as a physical address. On the other hand 8B
If the size of the unit block in the 8B area is read, it is determined whether it is a word at 32, a word at 16, or a word at 8, and calculations are performed for each setting value to obtain the page value. In other words, if 32 is a word, multiply the segment number by 4, if 16 is a word, multiply the segment number by 2 and add 4, and if 8 is a word, add 6 to the segment number.
Add to get the page value. Then, the page value and logical address are outputted to the physical address bus B as described above, and the process returns to the first step.

(2) Effects of the Invention As explained in detail above, according to the present invention, when the memory is expanded, the expandable capacity of the memory does not change depending on the size of the SB area, so there is no need to be particularly conscious of the size of 8B, and the memory This has the effect of allowing continuous access to physical addresses.

[Brief explanation of drawings]

Figure 1 is a diagram showing the contents of a physical address in the conventional address extension method, Figure 2 is a diagram showing the correspondence between logical addresses and physical addresses in the case of memory address fingers and toes, and Figure 3 is the concept of the present invention. Figure 4 shows the contents of the 20-bit physical address in the embodiment of the present invention, Figure 5 is a conceptual diagram of the address extension mechanism in the embodiment of the present invention, and Figure 6 shows the address in the embodiment of the present invention. The circuit diagrams of the expansion circuit, Fig. 7, Fig. 8, and Fig. 9 are correspondence diagrams of logical addresses and physical addresses when 8B is 32 words, 16 words, and 8 words, respectively, and Fig. 10 shows the present invention. FIG. 11 is a conceptual diagram of the case of implementation using a curvature gram, and FIG. 11 is an operational flowchart of FIG. 10. 1 in the middle is an extended memory address finger/toe area, 2 is a logical address area, 3 is an area for determining whether the address is within OB or 8B, 4 is a μ processor, 5 is an address expansion circuit, and 6 is 1
Megawords of memory, 7°8.9.17-1.17-2
．． 17-3.19-1 to 19-7.21-1 to 21-3
is an AND circuit, 10°18-1, 18-2, 20-
1 to 20-3 are OR circuits, 16-1 to 16-3 are NOT circuits, 11 is a page register reading section, 12 is a page register writing section, and 13 to 15 are control circuits according to the size of the 8B area. The setting key, R1, is the resistance. ! /Naru Pz mouth!

Claims (1)

[Claims] The main memory is divided into a common section and a plurality of segment blocks of a predetermined size, and page values are attached to the segment blocks. Output the data with the minimum number of bits (m bits) required to represent the value, and use the address extension means to directly convert the physical address of the main memory device if the skeleton logical address specifies an address in the common part. and when a segment block is specified, the m bits are added to the upper part of the minimum number n bits necessary to specify the address of each segment block area to form the physical address of the main storage device. address extension method.