JPS58131818A - Alternating current switch circuit - Google Patents

Abstract

PURPOSE:To open and close a switch arclessly at all times to any load, by providing the 1st and the 2nd delay circuits in a pulse generating circuit. CONSTITUTION:A pulse generating circuit 400' is provided with a series circuit consisting of a resistor R1 connected in parallel with an AC power supply AC of a main circuit 100 and a primary winding T1 of a transformer T as a voltage detection means, one end of a secondary winding T2 is grounded and a capacitor C1 and a slicer D2 eliminating high frequency components are connected in parallel with the T2 and a rectangular wave shaping circuit 401 is connected to the output side of the D2. The 1st differentiation circuit 402 and the 2nd differentiation circuit 403, similar differentiation circuit as 402, to the input terminal of which an inverter is connected, are connected in parallel with the output terminal of the circuit 401. The circuit 402 generates an ON-pulse of relay switches S1, S2 and the 1st delay circuit 405 is connected to the output side. Further, the 2nd delay circuit 406 is connected to the output side of a differentiation circuit 403 generating an OFF-pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates to an AC switch circuit, and more specifically to a switch circuit interposed between an AC source and a load that prevents arcing between contacts that open and close. ○ A circuit like the one shown in Figure 1 has already been proposed as this Yuzu's father tAc switch circuit. What is its configuration? To explain, in the same figure, -C100Ta is the main circuit to control opening and closing, 200 is the first relay drive circuit, 300 is the second relay vtA working circuit, and 400 is 9. ON synchronized with current power supply voltage
- A pulse generation circuit that outputs an OFF pulse, and a relay control circuit 500 that controls the valley relay drive circuits 200 and 300.

First, the main circuit 100 has a load LD? on both ends of the father fJrt and the electric wire AC. ! - through the diode D, the first relay switch S1 is connected to the column circuit, and the second relay switch S2
and are connected in parallel.

The first link drive circuit 200 that turns the first relay switch S, vON, OFF'' has a DC voltage and the first to sixth transistors Tr, to Tr6, which are reversely connected to each other.
A pair of Zener diodes ZD,
The relay switch 81 consists of a single-winding latching relay relay coil LyI, and the second glue race inner 82 is ON, 0FF-1! 'L@2 relay body disconnection circuit 300 is configured such that the DC current transistor and the seventh to twelfth transistors Try to 'rr12 are reversely connected to each other.
The second relay switch 82 consists of a pair of Zener diodes ZD2 and a relay coil Lyt of a 61-wound latching relay.

The pulse generation circuit 400 includes a first pulse generator. Second relay drive circuit 2
00, 300 (Z operation and valley relay seat 8
1.82 The ON pulse and OFF pulse to obtain the control signal that turns all ON and OFF are the same as the AC voltage.
This is caused by the resistance R1 connected to the main circuit 100, the primary winding T of the transformer T, and the secondary winding HT2.
, capacitor C1, and diode parallel slicer D2
, a rectangular wave shaping circuit 401, and a differentiation circuit group 404. The differentiation circuit group 404 consists of a differentiation circuit 402 that generates an ON pulse, and a differentiation circuit 403 that generates an OFF pulse.

The V-control circuit 500 has an ON pulse, an OFF pulse, and a load JLD7. (ON, OF'F) In response to the command signal, the first and second relay drive circuits 200
, drive 300! It outputs a control signal for ItII, and has a command signal input terminal 501, an inverter 502,
506, 508, and the first to first O ant gates AND, ~AND+.

, Noaketo NOR, and 1st work@2 orake)
It is composed of OR+, OR2, first to third time-limiting circuits 503, 505, 509 such as single female fixed multipliers, a delay circuit 504, and a buffer 510.

However, the 7th work is the 8th anime game ()AND? .

The output terminal of A N D8 is connected to the second relay body circuit 300.
~ANI)+n output terminal is the 11th) Leh brain movement circuit 20
0 respectively.

FIG. 2 is a timing chart showing the operating state, and in the same figure, the valley chart shows all the outputs of the parts corresponding to the symbols attached to the left end of each component, among which SI + '
)2 is the first. a second relay switch S;

The operating state of S2 is shown, and IL in the box shows all negative currents.

To explain the operation briefly, after the command signal changes to H level to turn on the load at time t, the first
The first glue race S1 is connected via the relay drive circuit 200.
or ON, then AND? Turn on the output of the L9 second glue race. Except for this, when the first relay seat 5l(2) is ON, the AC voltage W is reverse biased to the diode 'D, so no current flows through the relay switch S1, and no arc occurs. When the second glue race S is turned on, the diode D is turned on.
1 is a forward bias, but the voltage applied to the relay switch S2 is only the voltage drop of the tie auto D1 and does not reach the arc generation voltage, so no arc occurs.

Next, when the command signal goes to L level at time t2, the AND gate A N D
8 output ↓9 second relay switch S2 is 0FFL,
Thereafter, the first relay switch S, or 0FFj is turned on by the output of the antenna A N D+o. Therefore, when the second relay switch S2 is OFF, the diode D is forward biased, and when the first relay switch S2 is OFF, the diode D is reverse biased, so that the power is quenched without arcing. is possible.

In this circuit, the delay circuit 504 receives the positive ISγ phase of the current voltage 12IjI from the differential circuit group 404 through the respective ANDs ANDs and OR2. , for shifting the phase by △tfC at the negative phase VC1, and cn is for interposing the transformer T.
Since the phase of the output from the secondary side is different from C and the phase of the power supply voltage is different, it has the meaning of calibrating the full normal position of the phase at which the ON pulse should be generated and the F pulse.

However, since this circuit has a single delay circuit 504, it has the disadvantage that the phase cannot be shifted separately for the ON pulse and the OFF pulse k (Iffi).In other words, when the load LD is a resistive load, the voltage of the current Since the phase of the load current is in the same phase, there is no problem.If the load LD is an inductive load or a capacitive load, the phases of the power supply voltage and load current are different, so there is a phase shift between the ON pulse and the OFF pulse. The following problems arise regarding this.

First, when turning on the relay, the current does not flow n, so as in the conventional case, the first relay switch S is turned on during a half period of the reverse bias of the diode D, and the second relay switch is turned on during the same half period of the reverse bias of the diode D. There is no problem in considering only the voltage phase to turn on 52v. However, when the relay k is turned off, negative #box, #t, or current flows.
These currents have a leading or lagging phase than the voltage ↓ due to the characteristics of the load LD. In other words, even if the voltage is forward biased with respect to the diode D, the load current does not flow. In some cases, or conversely, there are cases in which load current flows even though the voltage is reverse biased. In these cases, is it only the voltage phase? Il-Think and relay'! ! If each relay drive circuit is operated so as to turn the relay to -0FF, the load current OFli'L may not be obtained in an appropriate phase, and there is a possibility that arc-free switching may be completely lost.

Therefore, when turning 1 OFF, there are eight ways to consider the phase shift of the ON pulse and OFF pulse based on the phase of the load current. When the relay is OFF, the phase of the load 'tJL flow is shifted to
ON pulses and O pulses that phase shift the FF pulses.
A circuit that can phase shift the FF pulses individually is required.

This NRC was proposed in view of the points mentioned above, and its purpose is to install a first delay circuit, a second delay circuit, and a pulse generation circuit within the pulse generation circuit, and to eliminate resistance loads, conductive loads, valley connections, etc. gender, etc.
ON pulse depending on the nature of negative Tae.

The OF''F Hals is configured to be turned ON and OFF at the appropriate phase of voltage and current by individually phase-shifting the delay circuit 11, and is always switched without arcing for any load. The purpose of the present invention is to provide an AC switch circuit that can open and close the circuit.

The present invention will be explained below with reference to the drawings.

FIG. 3 shows a first example of the present invention, the configuration of which is a main circuit 100 for opening/closing control, a first relay drive circuit 200,
Second relay body circuit 300. ON pulse.

It is roughly divided into a pulse generation circuit 400' which generates an OFF pulse, and a relay control circuit 500'.

First, the structure of the main circuit 100 is the same as that of the conventional example.

Furthermore, the construction of the first relay drive circuit 200 and the second relay drive circuit 300 are completely the same as the conventional ones.
In the first relay brain movement circuit 200 that causes the relay race Sr k ON , OF F', the ninth 77
) The base of the transistor Tr+l'Ir2 is connected to the output terminal of the gate AND, with all the resistors connected.
, the emitters of these transistors Tr, , Tr2 are grounded, and the collector of the transistor Tr+ is connected to the source of blood flow through a resistor, and the collector of the transistor Tr+ is connected to the source of blood flow through a resistor. The emitter of the transistor Tr3 is connected to the base of the transistor Tr3, and the emitter of the transistor Tr3 is connected to the current power supply VL:.

- 10,000, all resistors are connected to the output terminal of the 10th AND gate ANDIo, and the bases of transistors Tr4 and Tr6 are MlgGn, and these transistors Tr4 g T
The emitter of r6 is grounded and the transistor Tr
The collector of 6 is directly connected to the power supply through a resistor C1, and connected to the base of the transistor Tr6 through all resistors.
tt'z*) Uy The emitter of sister Tr6 is DC power supply V
? - contact@, cram school n, teru.

Historically, transistor Tr3. Between the connection point of each collector of Tr4 and the connection point of the valley collector of transistor Tr6, 'l'r+, there is a pair of Zener diodes ZD connected in reverse to each other, and a first relay switch. The relay coil Ly1 of the single-winding latching relay in S+ is connected in parallel.

2nd glue lace Ituna 82k ON, OFF 2nd
The configuration of the relay drive circuit 300 is the first relay drive circuit 20
Although it is exactly the same as 0, the connection state is omitted, but this relay drive circuit 300 has a transistor Try~'
1rt2 + Zener diode Z D2, 2nd glue V-switch 5tkL2 (moving relay coil LV2
and force).

Next, to the pulse generating circuit 400', the AC power supply A of the main circuit 100 is connected in parallel with the CVC, and a series circuit consisting of a resistor R1 and a primary winding T+;p'' of a transformer T serving as a voltage detection means. A capacitor C7 and a diode parallel slicer D2 are connected to ground one end of the secondary winding T2 of the transformer T, and are connected in parallel to the secondary winding T2 to remove the high frequency component of the output of the secondary winding Tt. The output terminal 17c of the rectangular wave shaping circuit 401 is connected to the output terminal 11111 V of the slicer D2 (the rectangular wave shaping circuit 401 consisting of an amplifier, a comparator, etc.) is connected to a capacitor, a resistor, or a diode. A first differentiating circuit 402 consisting of a differentiating circuit 402 and a second differentiating circuit 403 connected in an inverter to the input terminal of a similar differentiating circuit are connected in parallel. Furthermore, in FIG. 3, it is also 111 north that the first differentiating circuit 402 is constructed by a differentiating circuit group 404' consisting of an impark, a Noah gate, and an anchor.

Here, the differentiating circuit 402 is connected to the valley slope S1°S2.
A first delay circuit 405 is connected to the output 111 of the ON pulse, and the OF
On the output side of the differentiation circuit 403 that generates the F pulse, a second
A delay circuit 406 is connected.

RiTgee! + 1, 2nd IJ V-IMIQ
Times Wr 200, 300 K11l@@? The relay control circuit 500' that outputs negative LD'kON, OFF
The signal input terminals 501 are provided with 501 input terminals for inputting a command signal to be input, and the signal input terminals 501 are input terminals for inputting input signals such as an input terminal (a first AND gate, an AND gate, a second AND gate), an AND2 . The input terminal of the 7th input and the 9th AND?
, ANDo and the output terminal of the inverter 502 are respectively connected to the input terminals of the ANDo.

Connected to the input terminal of the maker's output NOR
1 and one input terminal of the third AND gate AND8. The valleys of the input terminals are connected to the input terminals, respectively.

The valley output terminals of the first AND and NOR are connected to the respective input terminals of the first OR, respectively. connected to the second terminal, its output terminal is the second. Third AND gate AND! .

It is connected to the input terminal of ANDs.

The output terminal of the second ant gate AND2 is connected to the input terminal of the fourth ant gate AND2, and the other input terminal of this ant gate AND2 is connected to the output terminal of the previous division circuit 402. At the same time, the output terminal of the third AND gate AND3(/, J is connected to one input terminal of the fifth AND gate ANDI+).The other input terminal of this AND gate ANDI+ is connected to The output terminal of the copy circuit 403 is connected to 0. ing.

A second time limit circuit 505, like a monostable multi-type circuit, is connected to the output terminal of the fourth and fifth antenna ANDs, and its output terminal is an inverter. 5060 input terminal, 8th AND gate ANDg and 9th AND gate
1 - AND, the valley of - is connected to the input terminal. The output terminal of the inverter 506 is the sixth AND,
Connected to the -10,000 input terminal of RL and AND GO) AN
Inverter 508 that constitutes differentiation circuit 507 together with D6
is connected to the other input terminal of the AND gate ANDa through the seventh and first O ANDa.
q, AND+. A third time-limiting circuit 509 such as a monostable multi-channel circuit is connected to the output side of ANDa, and
The output terminal of the Lπ buffer 510 connected to the output side of the delay circuit 504 is connected to the input terminal of this time limit circuit 5090. ,.

0 connected to the input terminals respectively, so the 7th
The output terminal of ANDq is connected to transistor Tr7. +
At the base of 1tr♂, the output terminal of the 8th analog (AND) is also connected to the transistor Tr+o+11+r,...
On the base of the 9th anime game) ANI), the output terminal is the first relay drive! The resistor of vlltJ path 2()0bi' is the transistor Tr, , the base yc of Tr2,
10th AND gate ANDI. The output terminals of the transistors are also connected to the bases of the trans/meta Tr4, Tr, .

Next, I will explain in detail with reference to the timing chart of the fourth problem in this operation.In FIG. Of these, Sl and S2 are the 1st.

The operating state of the second glue race suite bl l S2 is shown, and ``L'' discharges the negative charge #C, respectively.

1'1 As shown in Figure 3, the first. 2nd glue race iina s
, , and 82 are both OFF, the voltage of the AC illumination is as follows: transformer T, diode parallel slicer D
2nd place Kanakura, square wave shaping circuit 4 A square wave is output from the old C
Ru. At the rising edge of this square wave, the single-power differential circuit 402 in the 9T differential circuit group 404 outputs ON /<, )res.
, Also, at the falling edge of the rectangular wave, O is output from the other differentiating circuit 403.
Outputs FF pulse. Here, the ON pulse is phase-shifted by Δt at a position 1 synchronized with the positive phase of the AC power supply voltage through the delay circuit 405V. Is this 2 of Trance T?
: Since the phase of the side output or the phase of the AC power supply voltage is skipped, there is peace of mind that the phase of the ON pulse is also calibrated to the normal position.

Similarly, the OFF pulse is calibrated to a position synchronized with the negative phase of the load current by phase shifting rl across LvΔt in the delay circuit 406. Note that the delay time Δt2 always exceeds 0 depending on the properties of the load LD (inductive, capacitive, etc.) as described later, that is, the OFF pulse also occurs in synchronization with the AC power supply voltage, and the load LD is Since the phase of the non-load power supply voltage and the negative phase do not match due to the nature of the negative iLD, it is necessary to correct the phase to a normal phase by taking into account this phase difference sound.

At time t, the command signal at signal input terminal 5 (11) is applied to load L.
D k 01'', when it reaches the H level, at the rising edge, a pulse is output from the OR circuit OR+.This pulse is passed through the next stage time limit circuit 503 and is output for one period of the AC voltage #AC. This pulse and the command signal are passed through the ant gate AND2, and only the pulse generated by the rising clock pulse of command number 46 is output from the ant gate AND2.
Ru. This pulse and the output pulse of the delay circuit 405 are AND4k, so that one ON pulse is properly L, and this ON pulse is output to the OR gate 0Rt.
The output pulse width W2 of the time limit circuit 505 is 9. The output pulse width W2 of the time limit circuit 505 is the half cycle of the current pressure. yc temple setting n, 1st glue race suite 81
After the second relay switch S2 is activated, the time limit circuit 509 generates a pulse having a pulse width Wsk long enough for VC to operate the relay. However, if the pulse m Wsu Wa <,
It is necessary to satisfy the relationship of 0.
The nZ differential circuit 507 generates a positive clock pulse at
can also be configured as C-R. This clock pulse is input to the time limit circuit 509, and the output of the pulse width W3 is obtained. The output is passed through AND, and its output is used as the set signal of the first relay circuit S, and the transistors Trl and Tr of the relay drive circuit are connected.
t is added to the base of transistor T (by L)
r+, Trtl Tg is on during W3, current flows through the relay coil Lyl, and after mechanical operation time W4, the first relay switch S, turns 0N-j, the output of the time limit circuit 509, and the time limit circuit The inverted output of 505 and the command signal are connected via ANDv k, and the output is sent to the transistor Try + 'I' in the second relay drive circuit 300 as a set signal of the second relay switch S2.
rs, and the transistor Tr + Trs rTr
, is on for a period W, and a current flows through the relay coil Ly2 fL, and the time delay n. After w, the second glue race
2 turns on.

That is, when the first relay unit S1 is ON, the AC power supply voltage is reverse biased with respect to the diode D.
Relay switch 5IVC current does not flow and no arc occurs 01 Trap, when the second relay switch S2 is turned on, is the diode D1 forward biased?1 The voltage applied to the relay switch S2 is equal to the voltage drop of the diode D1.
Since the arc generation voltage VL is not reached, an arc will not occur. When the zero-order command signal reaches the L level at time t2, the falling voltage OR) OR, is the pulse t1% time limit circuit 503?

Then, a pulse with a pulse width W, is obtained. And Kate AN
At D3, the inversion command signal and the output of the time limit circuit 503 are combined, and a pulse with a pulse width W1 is obtained. This pulse and the OFF pulse as the output of the delay circuit 406 are AND, VC$ -Ite Logic-samakatara n
, or K) From OR2, the only OF'Ii' pulse is output from Samurai (L). After that, the same process as described above is performed, and in the , the output pulse VC, J:
, p transistor '1r in the second relay drive circuit 300
lo l 1rll * Tr, 2 is 0) J and relay coil Ly2 has 1 current in the direction opposite to the front rudder. OFF
do. ] Trap, and gate AND,.

The output pulse of 9th and 11th. Ru-Kakeru! gI] circuit 200
Transistors Tr4 * Tr5+ Tra are ON
t, After the current rL, W4 flows through the relay coil Ly+ in the direction opposite to that of the front rudder, the first relay switch S1 is turned off.

In this example, the second delay circuit 406
The delay time of the OF F' pulse can be set up independently, and using such an OFF pulse, AND II
After the period Ws, the second relay switch 82 is turned to O.
FF and AND gate AND+. via period W
After 4, the first relay switch S is turned OFF, so the first LD, resistive load, inductive load, and each output are negative. Or diode D
, in the forward half cycle, the second (/J relay switch S2k OF
The C-th relay switch S can be turned OFF', and together with the action of the first delay path 405, opening and closing can be performed without arcing.

In other words, as shown in the fifth example, when the load LD is a resistive load (see (a)), when it is an inductive load ((b)
), ↓, and in the case of a capacitive load (see (c)), even if the case is in example n, the phase of the ON pulse can be modified in the delay circuit 405 and the phase of the ON pulse can be changed by VC. In addition to being able to open the switch at an arc, the phase shift of the OFF pulse @ Δt and rl (phase shifted by the delay circuit 406 as shown in (C) in the figure) is the output pulse of the delay circuit 406. Then, the load current σ shown in (d) in each figure shifts to a negative half cycle, and finally the second and first relay switches Sl + S2 are turned off in the f phase as described above. 0 In addition, in Figure 5 (If-Hold), (a) shows the waveform of the AC power supply box, and (b) shows the phase shift of the operating element of the delay circuit 405, that is, the ON pulse. state, (C) is the delay circuit 406
In other words, the phase shift state of the OFF pulse is shown in Figure 9, (b), and (C). It shows.

In addition, -α and α are the 0th order 6th, which indicates the phase difference of voltage and current.
The figure illustrates a second example of the invention.

The only difference from the first example is the configuration of the pulse generation circuit 400'', and the other main circuits, the first and second relays @ A-off 1
01 road 200, 300, and relay control circuit 500
The configuration of ' is shown in the figure because it is exactly the same as the first example.

Both ``I'' and ``Imima'' are omitted.

Similarly to the first relay, the pulse generating circuit 400 has a tie-auto parallel slicer l)2. capacitor C1 on the input side.
, transformer T, resistor R, -=connected (a capacitor on the output side of the rectangular wave shaping circuit 401).

A single differentiating circuit 407 consisting of a resistor and a tie is connected to the ground, and a first . ! The two delay circuits 405' and 406' are connected in parallel with each other, and the output terminal of the delay circuit 405' is connected to the output terminal AND4, and the output terminal of the delay circuit 406' is connected to the AND6
V is connected. Note that 407' indicates another embodiment of the differential circuit. In other words, in the timing chart (see Figure 7), the output pulse of the rectangular wave shaping circuit 401 is shown in Figure 9. ” From the circuit 407 to 1
) /'Rus Qi-9-'fl (4j Teori, (-
rl, '1 * extension 1 m 405', set g t and mut, or phase shift (JN Hals and delay circuit 40B'VC, k > rl 'a rl 7
com t2/Koke phase shift-c u h' F pulse force 4
(6 things 1, healthy - (Hat, lm t2 is independently 1: + lit vc set nail yushi round 1ζ, same as the first L, negative 4:; (L D The relay switches S+ and Sdi can be opened at the optimum timing corresponding to the property of Vc.

The eighth example is Shibutokai 7r<-j-, which is the third example of the present invention.

This pulse generation circuit 400''σ] is still waiting, and the configuration in November is exactly the same as the first and second examples. Circuit 4 ()
C is the output side VC 1st delay circuit 405 of the side 4VC of the 2nd side 407, 40
6” When connected to 1j, VC1 delay 1μm path 40
5"(/J output terminal bus Ant. ANI) 4, and also the output terminal of delay circuit 4()b" Ant.
I).

This circuit 405's VC circuit is a differential circuit 407 (/J output pulse, t1 phase shift I, O pulse or 11%, so this ON pulse is delayed circuit 4.
06″ to study history △t2 or slow study T OF F
Pulse is Samurai. Accordingly, -C△tl +△t By setting 2 commutations, Figure 9 (a), (b), (c)'') Mt
l (Same as above, yC output phase increase relay switch S7.
St can be turned ON and OFF, resulting in arc-free opening and closing. Figure 9 (a) shows the lifting platform for the visiting load, (
(b) is a capacitive load, (c) is a resistive load, 69 s valley kakko, (a) is a father charging ratio type, (b) is a differential circuit 407
The output peak (e) is the output of the delay circuit 405'', and the output peak (d) of the delay circuit 406'' is the load current wave.

l, Konoshi II +71L↓, slow da 1;
, is selected at the time when the output sound of the differential circuit 4.137 is ON1 or 0F pulse at the smallest 111, and △t2 is the generation of ON pulse and 0F pulse. Set the time difference v to be
When the pulse of 7 was outputted, the inter-picture suppression was 1 jo, and at the time of transport, Oheno Rusu fireflies were generated, 1ri41; < t
If we add 4 to the field that generates the OF F pulse at tt, then at the second tail we get Mtl ''' tm +△L2= t,
10t,, in this 'f911, m1. = 11n, mu L
22j+>t, 1ζ, m, the 11th of t1 and △t2 in this example also becomes smaller, and the total capacitor of delay circuit 405'', 406''l) J The capacitance of the capacitors can be reduced, and the delay circuits 405" and 406" can be made smaller.

It should be noted that Figure 1 is a timing chart showing the operation of the entire circuit.

As described above, according to the invention, the first delay circuit is connected to the second delay circuit to generate pulses.

The ON pulse and OFF pulse are individually phase-shifted by the front hole delay circuit in response to the inductive load, yado load, and negative current to determine the voltage of each relay switch and to control the current flow. phase -
Since the VC is designed to turn ON and OFF, the switch can be opened and closed without arcing under any load.

[Brief explanation of drawings]

Fig. 1 is the Ig circuit diagram of the promotion rice mogul, No. 21z1 is the timing chart as well, Fig. 3 is the circuit diagram showing the first example of non-invention, Fig. 4 is the 10'' timing chart, and No. 5 is the timing chart.
(), (b), and (c) are the same actions
1 Nu 1 is the second example of non-invention, Shikitsu Shoji 1 Circuit 1 Me 1, 7th Evil is also the timing chart, 8th Evil VJ, Moku Aemon's 3rd 1 Kuri Ke 2 Ro 11 [7J〈
Fur M Road Ward 1, Tribute ↓ 9 Closed Buy),
(b) and (c) are rotating floor plans, 10th section 1
is also a timing chart. 100... Main circuit, 200... First relay drive circuit, 300... Second relay -
#A4 moving Romi' road, 400', 4
00'', 400'''...Pulse generation circuit, 500'...Relay control circuit, AC/
... Bunryu Amaga, LL) ... Load, D, ...
...Diode, SH...First glue race, S2...Second glue race, T
...Transformer, 401...Square wave shaping circuit, 402, 403, 407, 407'...
... Differentiation circuit, 404, 404'... Value division circuit group, 405, 405'. 405″...first delay circuit, 406, 40
6', 406"...Second delay 1 circuit timer Applicant: Matsushita%, Kousaku Shiki Company ■〒 -92-

Claims (1)

[Scope of Claims] (1) Alternating current (N) is connected in series to the negative, tie, first glue race, and k+, and is parallel to the series circuit of the first glue race. The main circuit is connected to the second glue race, and the main circuit is equipped with a transformer for detecting the voltage of the alternating current and AC voltage.
II: First and second differentiating circuits are provided to generate ON pulses and OFF pulses synchronized with V, and a first delay and a second delay are provided to individually phase shift the ON pulses and OFF pulses, respectively. Between the pulse generating circuit comprising the circuit, the ON pulse via the first delay circuit, and the finger metal signal for turning on the negative voltage, a reverse current voltage is generated when the tie motor is reverse biased. A control signal for turning the first relay switch ON is generated through the first relay drive circuit, and after the first relay switch is turned ON, when the countercurrent power supply voltage is forward biased with respect to the diode, the second relay driving circuit valve is activated. The second glue race itte'kON
At the same time, a control signal is generated to cause a negative current to be generated between the OF''F pulse through the second delay circuit and a command signal to cause a negative current to be generated by the tie auto VC.
At the same time, a control signal is generated to turn the second glue race OFF through the second relay secretion circuit,
After the second glue race is turned OFF, the load current is reversed to the diode VC, and the first relay body circuit is simultaneously activated to turn the first glue race OFF! L
A relay control circuit that generates a control signal and a countercurrent switch circuit. (2) Countercurrent galvanic erosion and negative current J and diode are connected to the first glue race and the violet array, and the VC1 is connected to the diode, and the second is connected in parallel to the series circuit of the first glue race.
The main and old circuits are connected to the relay switch of 1, and the circuit of 11 is connected to the main and old circuits, which detects the voltage of the main circuit, and generates pulses that are cycled to the reverse current source and voltage. #jλ
-The first phase of a major individual VC phase shift with Harusuke Maeda
A pulse generation circuit comprising a second delay circuit, an ON pulse with the first delay circuit fully valved, and a negative circuit ON.
A command signal to get pregnant! :r), the first relay is driven 1 when the AC power supply voltage is reverse biased with respect to the previous nth diode!
Generates a control signal that closes the first relay switch 1ON-1r through two circuits, and
, if the father tAt and the current W voltage are forward-biased to the diode, a control signal is generated to turn on the second relay circuit through the second relay drive gl circuit, and at the same time, the second delay circuit is turned on. In response to the OFF pulse and the command No. 1h to turn off the load, a control signal is generated which activates the second relay drive circuit when the load current is in the forward direction with respect to the diode and causes the second relay to start 'k OF li'. 〃When the load current is in the opposite direction with respect to the diode when the second glue race is turned off, the first glue race is turned off through the first relay drive circuit.
An AC switch circuit comprising a relay control circuit that generates control No. 16 that causes OF f'', and a t. The second VC is connected in parallel to the series circuit of the first relay switch.
The main circuit formed by connecting the relay switch of
, a single differential circuit that detects voltage bias and generates pulses synchronized with AC power supply voltage.
At the same time, a pulse generation circuit comprising a first delay circuit and a second delay circuit connected in series to the output side of this differentiating circuit, an ON pulse with all the first delay circuits, and a load 7. (
When the AC power supply voltage is reverse biased with respect to the diode VC, the first relay is driven 1u by the command No. 4g to turn ON.
The control side turns on the first relay switch.
generates a signal, and after the first relay switch is turned on, generates a control signal that causes the second relay raceway k O, N through the second relay drive circuit when the AC power supply voltage is forward biased to the diode. At the same time, the second delay circuit connects the Ofi' F pulse and the load to O.
When the load current is applied to the tie motor in the forward direction, a control signal is generated which causes the load current to flow through the second link drive circuit to the second linkage current i0F'F in the forward direction. After the second relay switch is turned off, the load current flows into the diode and the first relay switch is turned off in the reverse direction.
The first glue race is connected through the relay drive circuit.
F-+! : An AC switch circuit comprising a relay control circuit that generates a low control signal.