JP2003244945A - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator that can reduce switching loss according to a load value. <P>SOLUTION: The regulator has a plurality of switching transistors 1, 2, with differing W/L values, a switch element 7 that can select a connected or disconnected state for gates on the switching transistors 1, 2; and a control circuit 6 that controls the ON/OFF of the switching transistors. Further, the switching element 7 outputs a signal that selects the connected or disconnected state of the gates on the switching transistors 1, 2 depending on a signal from the outside. By this means, switching is performed by a switching transistor 1 or 2 that has an optimum W/L for a fluctuating load. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching regulator capable of selectively using a plurality of N-chMOS transistors provided in advance as switching transistors.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional step-up switching regulator with a built-in switching transistor. In the step-up switching regulator with a built-in switching transistor, the N-ch MOS switching transistor 1 is located inside the switching regulator IC 33. Dividing resistor 3
The potential difference between both ends of the load resistor 19 is monitored by 4 and 35, and this is compared with the voltage value of the reference voltage 38 by the error amplifier 36. The control circuit 6 outputs an oscillation waveform for ON / OFF control of the gate voltage of the N-ch MOS switching transistor 1 based on the comparison result of the error amplifier 36.

When a voltage higher than the threshold voltage of the N-chMOS transistor (hereinafter referred to as "H") is input to the gate of the N-chMOS switching transistor 1, the N-chMOS switching transistor 1 is turned on and the current Is the voltage source 3
2, coil 4, N-ch MOS switching transistor 1,
The current flows through the path of the power supply terminal 3 at the negative level or the ground level and the current flowing through the coil 4 increases. Since the current flowing through the coil 4 increases, energy is stored in the coil 4. At this time, the current flowing through the load resistor 19 is
Since it is not supplied from the voltage source 32, it is supplied from the output capacitor 39 and the output voltage value decreases. This operation is called a first operation mode.

On the other hand, when a negative level or ground level voltage (hereinafter referred to as "L") is input to the gate of the N-chMOS switching transistor 1, the N-chMOS is turned on.
The switching transistor 1 is turned off, and the current flows through the voltage source 32, the coil 4, and the diode 5.
In the first operation mode, the energy stored in the coil 4 is supplied and the output voltage value rises. This operation is called a second operation mode. By alternately performing the first operation mode and the second operation mode, control is performed so that a constant output voltage value is obtained.

FIG. 9 shows a conventional step-up switching regulator with an external switching transistor. In the step-up switching regulator with an external switching transistor, the N-ch MOS switching transistor 1 is located outside the switching regulator IC 33. The basic boosting operation is the same as that of the conventional boosting switching regulator with a built-in switching transistor in FIG.

[0006]

In order to increase the maximum output current value, it is preferable to increase the W / L value of the switching transistor of the switching regulator, but the switching loss will increase. On the other hand, in order to improve the efficiency at light load, it is better to reduce the W / L value for the purpose of reducing switching loss, but the maximum output current value will be reduced. These two requirements are in a trade-off relationship. If there is only one switching transistor, there is a problem that the optimum W / L value cannot be changed according to the request.

[0007]

Means for Solving the Problems A plurality of switching transistors having different W / L values, a switch capable of selecting a connection or disconnection state of a gate of the switching transistor, and ON / OFF of the switching transistor.
And a control circuit for controlling the switch, and the switch outputs a signal for selecting a connection or disconnection state of the gate of the switching transistor according to a signal from the outside.

The switch receives a signal from the outside and a first transistor and a second transistor connected in series between the control circuit and a power source terminal of a negative level or a ground level, and the first transistor. And a shoot-through current prevention circuit that outputs a signal for controlling the second transistor, and an intermediate potential between the first transistor and the second transistor is applied to the gate terminal of the switching transistor. Therefore, the shoot-through current prevention circuit outputs a signal that is turned off to at least one of the first transistor and the second transistor.

It has a plurality of switching transistors having different W / L values, a fuse capable of selecting connection or disconnection state of the gate of the switching transistor, and a control circuit for controlling ON / OFF of the switching transistor. And a switching regulator.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION A switching regulator according to the present invention is provided with at least one or more switches which can be ON / OFF controlled electrically or mechanically in advance, or which is provided in advance. Further, there is provided means for appropriately providing a connection state or a disconnection state independently to at least one or more fuses.

By providing such means, there is a merit that the maximum output current value can be increased, but there is a demerit that the switching loss increases, and there is a merit that the switching loss can be reduced. It is possible to select electrical characteristics that have a demerit that the output drive current value becomes small according to requirements.

[0012]

FIG. 1 is a circuit configuration diagram of a switching regulator showing a first embodiment of the present invention. FIG. 1 is a conventional step-up switching regulator N-ch MOS of FIGS. 8 and 9.
It corresponds to the peripheral circuit of the switching transistor 1. The difference between FIG. 1 and the conventional step-up switching regulators FIGS. 8 and 9 is that the switching element 7 can electrically select the switching transistor by the voltage applied from the switch signal input terminal 8.

The electrical signal is input from the switch signal input terminal 8 to the shoot-through current prevention circuit 10. The shoot-through current prevention circuit 10 turns on both the N-ch MOS transistor 11 and the N-ch MOS transistor 12 at the same time in order to prevent shoot-through current.
The N-chMOS transistor 11 and the N-chMOS are prohibited.
This is a circuit for controlling ON / OFF of the transistor 12.

For example, the shoot-through current prevention circuit 10 is realized by the configuration shown in FIG. P-ch MOS transistor 14, N-
The chMOS transistor 16 and the resistor 15 form an inverter 13 with a delay function. Switch signal input terminal 8
When a voltage signal that changes from H to L is input, P-chMO
The drain terminal voltage of the S transistor 14 changes from L to H. The drain terminal voltage of the N-ch MOS transistor 16 changes from L to H at a timing slightly delayed from the timing when the drain terminal voltage of the P-ch MOS transistor 14 changes from L to H because of the resistance 15. When a voltage signal that changes from L to H is input to the switch signal input terminal 8, the drain terminal voltage of the N-ch MOS transistor 16 changes from H to L. The drain terminal voltage of the P-ch MOS transistor 14 changes from H to L at a timing slightly behind the timing of the drain terminal voltage of the N-ch MOS transistor 16 changing from H to L because of the resistance 15. By such operation, the N-ch MOS transistor 11
The state in which the N-ch MOS transistor 12 and the N-ch MOS transistor 12 are simultaneously turned on is prohibited. That is, by providing dead time, N-
The risk of a through current flowing through the chMOS transistor 11 and the N-chMOS transistor 12 is avoided.

When a voltage signal changing from H to L is input to the switch signal input terminal 8, a voltage signal changing from H to L is given to the gate of the N-chMOS transistor 11, and the N-chMOS transistor 11 is supplied. Is turned off. On the other hand, N-ch
A signal that changes from L to H is given to the gate of the MOS transistor 12 a little later than the timing when the voltage signal of the gate of the N-ch MOS transistor 11 changes from H to L. The N-ch MOS transistor 12 is turned on slightly later than the timing of turning off. At this time, the switching circuit controlled by the control circuit 6 is only the N-ch MOS transistor 1. When a voltage signal changing from L to H is input to the switch signal input terminal 8, the gate of the N-ch MOS transistor 12 is changed from H to L.
N-ch MOS transistor 1 given a voltage signal that changes to
2 is OFF.

On the other hand, the gate of the N-chMOS transistor 11 is supplied with a voltage signal that changes from L to H, slightly later than the timing when the voltage signal of the gate of the N-chMOS transistor 12 changes from H to L. , The N-chMOS transistor 11 is turned on slightly later than the timing when the N-chMOS transistor 12 is turned off. At this time, the switching transistors controlled by the control circuit 6 are the N-chMOS switching transistor 1 and the N-chMOS switching transistor 2
Will be both.

By this operation, the W / L value is reduced for the purpose of reducing switching loss at light load,
W for the purpose of increasing the maximum output current value under heavy load
It is possible to select whether to increase the / L value. It is obvious that the first embodiment can be implemented with the switching transistor built therein or externally.

FIG. 3 is a circuit configuration diagram of a switching regulator showing a second embodiment of the present invention. The feature of the second embodiment resides in that the switch element 7 is controlled by the output of a voltage detector (hereinafter referred to as "VD") 21. The value of the current flowing through the load resistor 19 is the load resistor 1
9 is input to VD21 as a potential difference across sense resistor 20 having a sufficiently small value, and VD21 determines whether the load is a light load or a heavy load.
H or L voltage signal is given. At this time, the VD reference voltage source 23 has an appropriate voltage value for the VD 21 to distinguish between a light load and a heavy load. Further, it is assumed that the VD reference voltage source 23 can be changed to a desired value. The operation of the switch element 7 is similar to that of the first embodiment. From the output voltage signal of VD21, N-ch MOS transistor 11 and N-ch MOS transistor 12
It is obvious that the same effect as that of the first embodiment can be obtained because the ON / OFF control is possible. It is obvious that the second embodiment can be implemented with the switching transistor built therein or externally.

FIG. 4 is a circuit configuration diagram of a switching regulator showing a third embodiment of the present invention. The difference from the first embodiment is that the switch element 7 is configured by a combination of a MOS transistor and a resistor in FIG. 1, but the switch element is realized by the mechanical switch 24 in the third embodiment. N-ch MOS by mechanical switch 24
The gate of switching transistor 2 and the gate of N-chMOS switching transistor 1 are connected, or N-chMOS
It is possible to select whether to connect the gate of the switching transistor 2 and the power supply terminal 3 of the negative level or the ground level. Gate of N-chMOS switching transistor 2 and N-chMOS switching transistor 1
When the gate of is connected, the switching transistor controlled by the control circuit 6 becomes both the N-chMOS switching transistor 1 and the N-chMOS switching transistor 2. When the gate of the N-chMOS switching transistor 2 is connected to the negative-level or ground-level power supply terminal 3, the control circuit 6 controls only the N-chMOS transistor 1. It is obvious that the same effect as that of the first embodiment can be obtained by controlling the ON / OFF of the mechanical switch 24. The above Example 3 is
It is obvious that the switching transistor can be either internal or external.

FIG. 5 is a circuit configuration diagram of a switching regulator showing a fourth embodiment of the present invention. The difference from the first embodiment is that the switch element 7 is configured by a combination of a MOS transistor and a resistor in FIG. 1, but the switch element 7 is realized by the fuse 25 and the fuse 26 in the fourth embodiment. . When only the fuse 25 is cut, the switching transistor controlled by the control circuit 6 is only the N-chMOS switching transistor 1. When only the fuse 26 is blown, the switching transistors controlled by the control circuit 6 are both the N-chMOS switching transistor 1 and the N-chMOS switching transistor 2. It is clear that by selectively disconnecting the fuses 25 and 26, the W / L value of the switching transistor can be selected in two ways, and the same effect as that of the first embodiment can be obtained. It is obvious that the fourth embodiment can be implemented with the switching transistor built-in or externally mounted.

FIG. 6 is a circuit configuration diagram of a switching regulator showing a fifth embodiment of the present invention. N in Example 1
Each of the -chMOS switching transistor 1 and the N-chMOS switching transistor 2 has been described as one N-chMOS transistor, but as shown in FIG. -chMOS switching transistor 28, N-chM
It is obvious that the same effect can be obtained by connecting two N-chMOS switching transistors in series like the OS switching transistor 29 and the N-chMOS switching transistor 30. It is obvious that the same can be said for other N-ch MOS transistors and P-ch MOS transistors used.

FIG. 7 is a circuit configuration diagram of a switching regulator showing a sixth embodiment of the present invention. In the first embodiment, the switching transistors are N-ch MOS switching transistor 1 and N-ch MOS switching transistor 2.
However, it is clear that the same effect can be obtained even when the N-chMOS switching transistor 31 is added and the number of N-chMOS switching transistors is three. In addition, the switching transistor is 3
It is obvious that the same effect can be obtained in the case of two or more.

[0023]

As described above, according to the switching regulator of the present invention, the switching transistor is constituted by the switching element to reduce the W / L value for the purpose of reducing the switching loss at the light load, or at the heavy load. It is possible to select the optimum W / L value according to the requirement of increasing the W / L value for the purpose of increasing the maximum output current value.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a switching regulator showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration example of a switch element.

FIG. 3 is a circuit configuration diagram of a switching regulator showing a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a switching regulator showing a third embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a switching regulator showing a fourth embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a switching regulator showing a fifth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of a switching regulator showing a sixth embodiment of the present invention.

FIG. 8: Conventional boosting switching regulator power supply circuit with built-in switching transistor

FIG. 9: Conventional boosting switching regulator power supply circuit with external switching transistor

[Explanation of symbols]

1, 2, 27, 28, 29, 30, 31 N-ch MOS switching transistor 3 Minus level or ground level power supply terminal 4 Coil 5 Diode 6 Switching regulator Control circuit 7 Switch element 8 Switch signal input terminal 9 Power supply terminal 10 Through current Prevention circuit 11, 12, 16, 18 N-chMOS transistor 13 Inverter circuit with delay function 14, 17 P-chMOS transistor 15, 19, 20, 34, 35 Resistor 21 Voltage detector 22 Voltage detector Error amplifier 23 Voltage detector Reference voltage source 24 Mechanical Switches 25, 26 Fuse 32 Voltage Source 33 Switching Regulator IC 36 Switching Regulator Error Amplifier 37 Switching Regulator Reference Voltage Source 38 Switching Regulator Oscillation Circuit 39 Output capacity

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5H730 AA14 BB14 DD04 DD13 DD17                       DD21 DD28 EE59 FD01 FG01                       FG23 FV03

Claims (2)

[Claims] 1. A switch circuit having a plurality of switching transistors having different W / L values, a switch element capable of selecting a connection or disconnection state of a gate of the switching transistor, and a control circuit for controlling ON / OFF of the switching transistor. Then, the switching element outputs a signal for selecting a connection state or a disconnection state of the gate of the switching transistor according to a signal from the outside. 2. The switch element receives a signal from the outside, a first transistor and a second transistor connected in series between the control circuit and a power supply terminal of a negative level or a ground level. A through current prevention circuit that outputs a signal for controlling the first transistor and the second transistor, wherein a potential between the first transistor and the second transistor is a gate terminal of the switching transistor. The switching regulator according to claim 1, wherein the through-current prevention circuit outputs a signal that is turned off to at least one of the first transistor and the second transistor.