JPS58131191U - Voltage doubler rectifier circuit - Google Patents
Voltage doubler rectifier circuitInfo
- Publication number
- JPS58131191U JPS58131191U JP2568582U JP2568582U JPS58131191U JP S58131191 U JPS58131191 U JP S58131191U JP 2568582 U JP2568582 U JP 2568582U JP 2568582 U JP2568582 U JP 2568582U JP S58131191 U JPS58131191 U JP S58131191U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- rectifier circuit
- doubler rectifier
- circuit
- voltage doubler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Rectifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の倍電圧整流回路の回路図、第2図は本考
案に係る倍電圧整流回路の回路図である。
1・・・・・・全波整流回路、2B・・・・・・検出回
路、3・・・・・・SCRを用いた倍電圧整流を行うた
めの回路、AC・・・・・・交流電源、cl、 c2.
c3. c、・・・・・・電解コンデンサ、D工、
D2. D3. D4. D6. D6. D7. D
9゜Dlo・・・・・・ダイオード、D8.Dll・・
・・・・ツェナ・ダイオ −ド、Ql・・・・・・制御
用トランジスタ、Q3・・・・・・電流増幅用トランジ
スタ、R1,R2,R3,R4,R5・・・・・・抵抗
、■・・・・・・ツェナ電圧、VBE・・・・・−Q、
のベース・エミッタ間電圧。FIG. 1 is a circuit diagram of a conventional voltage doubler rectifier circuit, and FIG. 2 is a circuit diagram of a voltage doubler rectifier circuit according to the present invention. 1...Full wave rectification circuit, 2B...Detection circuit, 3...Circuit for voltage doubler rectification using SCR, AC...Alternating current power supply, cl, c2.
c3. c,... Electrolytic capacitor, D engineering,
D2. D3. D4. D6. D6. D7. D
9゜Dlo...Diode, D8. Dll...
... Zener diode, Ql ... control transistor, Q3 ... current amplification transistor, R1, R2, R3, R4, R5 ... resistance, ■・・・Zena voltage, VBE・・・−Q,
base-emitter voltage.
Claims (2)
倍電圧整流用回路と、前記交流電源と前記倍電圧整流用
回路のSCRとに接続し交流電源電圧を検出しその検出
電圧の高低に応じて前記SCRをオン、オフする検出回
路とを備・え、直列接続されたコンデンサ回路から整流
出力を得るようにした電源回路において、前記検出回路
にその検出電圧に基づいて導通、非導通する制御用トラ
ンジスタと、前記検出電圧が印加され且つ前記制御用ト
ランジスタによって制御されるとともに前記SCRを駆
動するツェナ・ダイオードとトランジスタから、成る定
電圧回路とを設けることを特徴とする倍電圧整流回路。(1) A rectifier circuit connected to an AC power supply, a voltage doubler rectifier circuit using an SCR, and a voltage doubler rectifier circuit connected to the AC power supply and the SCR of the voltage doubler rectifier circuit to detect the AC power supply voltage and the level of the detected voltage. In the power supply circuit, the power supply circuit includes a detection circuit that turns on and off the SCR according to the voltage, and obtains a rectified output from a series-connected capacitor circuit. a voltage doubler rectifier circuit comprising a Zener diode and a transistor to which the detection voltage is applied, which is controlled by the control transistor, and which drives the SCR. .
ードに前記トランジスタのベースを接続して成り、前記
ツェナ・ダイオードのアノードと前記トランジスタのコ
レクタとの間に前記検出電圧を印加するようにし、前記
ツェナ・ダイオードの両端に前記制御用トランジスタの
コレクタ、エミッタを接続し、前記検出電圧を抵抗を介
して前記ツェナ・ダイオードのカソードに印加するとと
もに検出電圧の一部を前記制御用トランジスタのベース
に加え、前記トランジスタのエミッタを前記倍電圧整流
用回路のSCRのゲートに接続するようにしたことを特
徴とする実用新案登録請求の範囲第1項記載の倍電圧整
流回路。(2) The constant voltage circuit is configured by connecting the base of the transistor to the cathode of the Zener diode, and applies the detection voltage between the anode of the Zener diode and the collector of the transistor; The collector and emitter of the control transistor are connected to both ends of the Zener diode, and the detection voltage is applied to the cathode of the Zener diode through a resistor, and a part of the detection voltage is applied to the base of the control transistor. 2. The voltage doubler rectifier circuit according to claim 1, wherein the emitter of the transistor is connected to the gate of the SCR of the voltage doubler rectifier circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2568582U JPS58131191U (en) | 1982-02-26 | 1982-02-26 | Voltage doubler rectifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2568582U JPS58131191U (en) | 1982-02-26 | 1982-02-26 | Voltage doubler rectifier circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58131191U true JPS58131191U (en) | 1983-09-05 |
Family
ID=30037653
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2568582U Pending JPS58131191U (en) | 1982-02-26 | 1982-02-26 | Voltage doubler rectifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58131191U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60204264A (en) * | 1984-02-23 | 1985-10-15 | アールシーエー ライセンシング コーポレーシヨン | Power source |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5029247B1 (en) * | 1969-01-06 | 1975-09-22 |
-
1982
- 1982-02-26 JP JP2568582U patent/JPS58131191U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5029247B1 (en) * | 1969-01-06 | 1975-09-22 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60204264A (en) * | 1984-02-23 | 1985-10-15 | アールシーエー ライセンシング コーポレーシヨン | Power source |
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