JPS619932U - Reset signal generator - Google Patents
Reset signal generatorInfo
- Publication number
- JPS619932U JPS619932U JP9479484U JP9479484U JPS619932U JP S619932 U JPS619932 U JP S619932U JP 9479484 U JP9479484 U JP 9479484U JP 9479484 U JP9479484 U JP 9479484U JP S619932 U JPS619932 U JP S619932U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- voltage
- circuit
- emitter
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第１図は本考案の一実施例のリセット信号発生装置を示
す回路構成図、第２図は同リセット信号発生装置の動作
を示すタイムチャート、第３図は本考案の他の実施例の
リセット信号発生装置を示す回路構成図、第４図は従来
のリセット信号発生装置を示す回路構成図、第５図は同
リセット信号発生装置の動作を示すタイムチャートであ
る。
交流電源、２・・・電源トランス、３・・・整流回路、
５・・・直流安定化電源回路、６・・・負荷電子回路、
７．１７・・・トランジスタ、８．１４・・・コンデン
サ、９・・・抵抗、１０．１１・・・分圧抵抗、１２，
１３，１６・・・ダイオード、１５・・・補助電源回路
、Ｖど・直流安定電圧、ｖ８・・・ベース電圧（分圧電
圧）、Ｖｃｃ・・・電源端子、Ｒ・・・リセット端子。[Brief Description of the Drawings] Fig. 1 is a circuit configuration diagram showing a reset signal generating device according to an embodiment of the present invention, Fig. 2 is a time chart showing the operation of the reset signal generating device, and Fig. 3 is a circuit diagram showing the reset signal generating device according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing a conventional reset signal generating device, and FIG. 5 is a time chart showing the operation of the reset signal generating device. AC power supply, 2... power transformer, 3... rectifier circuit,
5... DC stabilized power supply circuit, 6... Load electronic circuit,
7.17... Transistor, 8.14... Capacitor, 9... Resistor, 10.11... Voltage dividing resistor, 12,
13, 16... Diode, 15... Auxiliary power supply circuit, V/DC stable voltage, v8... Base voltage (divided voltage), Vcc... Power supply terminal, R... Reset terminal.
Claims (1)
の整流回路の出力端に接続され、この整流回路の出力電
圧を直流安定電圧へ変換して負荷電子回路の電源端子へ
供給する直流安定化電源回路と、ベースに前記整流回路
の前記出力電圧を抵抗で分圧した分圧電圧が印加され、
エミツタに前記直流安定電圧が印加され、コレクタに前
記負荷電子回路のリセット端子が接続されたｐｎｐ型の
トランジスタと、このトランジスタの前記エミツタと前
記直流安定化電源回路の前記直流安定電圧の出力端間に
介挿されたタイオードと前記エミツタと接地間に介挿さ
れたコンデンサとて構成された補助電源回路とを具備し
てなることを特徴とするリセット信号発生装置。An AC power supply, a rectifier circuit connected to this AC power supply, and a DC stabilizer connected to the output end of this rectifier circuit that converts the output voltage of this rectifier circuit into a stable DC voltage and supplies it to the power supply terminal of the load electronic circuit. a divided voltage obtained by dividing the output voltage of the rectifier circuit by a resistor is applied to the base of the rectifying power supply circuit;
A pnp transistor whose emitter is applied with the stable DC voltage and whose collector is connected to the reset terminal of the load electronic circuit, and between the emitter of this transistor and the output terminal of the stable DC voltage of the stabilized DC power supply circuit. 1. A reset signal generating device comprising: a diode inserted into the emitter; and an auxiliary power supply circuit configured with a capacitor inserted between the emitter and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9479484U JPS619932U (en) | 1984-06-25 | 1984-06-25 | Reset signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9479484U JPS619932U (en) | 1984-06-25 | 1984-06-25 | Reset signal generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS619932U true JPS619932U (en) | 1986-01-21 |
| JPH0317473Y2 JPH0317473Y2 (en) | 1991-04-12 |
Family
ID=30653569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9479484U Granted JPS619932U (en) | 1984-06-25 | 1984-06-25 | Reset signal generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS619932U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190107563A (en) | 2018-03-12 | 2019-09-20 | 린텍 가부시키가이샤 | Temperature sensitive adhesive sheet and laminate |
-
1984
- 1984-06-25 JP JP9479484U patent/JPS619932U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190107563A (en) | 2018-03-12 | 2019-09-20 | 린텍 가부시키가이샤 | Temperature sensitive adhesive sheet and laminate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0317473Y2 (en) | 1991-04-12 |
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