JPS581309A - Gain control circuit - Google Patents

Abstract

PURPOSE:To suppress dererioration in the unbalance and nonlinearity of a double balanced circuit, by supplying a current to the circuit through transistors (TR) applied with a constant bias voltage. CONSTITUTION:The input signal from a signal source 11 is amplified by a TR1 and supplied to the emitters of TRs 3 and 4. Since the TRs 3 and 4 are controlled by a gain control voltage 25, the output signal of the TR1 is distributed to the TRs3 and 4 in accordance with the control, and then outputted through a TR8. A load resistance 26 develops a voltage which is constant in terms of direct current. This DC voltage is applied to the base of the TR8 to hold the base emitter voltages of the TRs 7 and 8 constant. Therefore, the collector emitter voltages of the TRs 3-6 all become equal to obtain a high degree of balancing.

Description

DETAILED DESCRIPTION OF THE INVENTION This paper relates to a gain control circuit and uses a double balanced circuit for s'f#.

Conventionally, gain control circuits using double-balanced circuits have been widely used because they provide stable operation, but F-oI
When the i-path is integrated into an integrated circuit, it is difficult to avoid variations in the characteristics of the transistor pairs constituting the balanced circuit. leads to undesirable results such as nonlinearity.

The purpose of the device is to provide a gain control circuit using a double balanced circuit with a high degree of balance.

According to the device @, input signal 4# is supplied to the base! l
a third common emitter transistor whose base is supplied with a bias voltage; and a third transistor whose collector output is supplied to the first transistor. , the gain control voltage is supplied to the base and differentially connected to the 30th transistor with the transistor No. 9, and the gain control voltage is supplied to the base and the collector is connected to the collector of the No. 3 transistor. 9) A 60th transistor whose collectors are connected to the collectors of the 9th transistor and the 3rd common emitter layer transistor, which are differentially connected to the transistor Sδ, and whose collectors are connected to the collector of the fIIi transistor; and a seventh transistor whose collector is connected to its collector and whose base is supplied with a constant DC bias voltage.

an eighth transistor whose collector is connected to the collector of the sixth transistor and whose base is connected to the base of the first transistor;

The present invention provides a gain control circuit characterized in that the gain control circuit has the following characteristics.

In the gain control circuit based on zero output, a constant DC bias voltage is supplied to the base of the ninth to eighth transistors.
S and 6th transistors and @4 to Kuzutsuta
Since the collectors of PJMK6 and PJMK6 are connected to each other, the collector voltages of the transistors of the fifth PJMK6 are approximately equal. Therefore, 5th vs. 11. Even if variations in characteristics occur in the 40th transistor and the transistors Eggs and @e, it is possible to suppress deterioration in operating characteristics such as non-linearity in one circuit.

Hereinafter, the present invention will be described in detail with reference to the following.

No. 1 is a circuit diagram showing one embodiment of the device.

The input signal gill is supplied via a coupling capacitor to the base of a transistor 10 which is grounded by a resistor 118. A bias voltage IJIX11 is supplied from a bias power supply 15 to the base of the transistor 10 via a resistor 1s, and this bias voltage is further applied to the base of the transistor 80, which is grounded through a resistor 24. is being supplied to.

/((7J electric @-15 has zero AC impedance, so the influence of the input signal on transistor 3 can be ignored, and transistor 3 is connected to the collector of transistor l.
, 40 electric power is connected to the power supply, and a transistor 3.4 Hiro differential amplifier S is configured. A 6.60mm transistor is commonly connected to the collector of transistor 3, forming a transistor 5°/6#i sliding amplifier. Transistor 4. The bases of the transistors are connected in common, the vias, and the bases of the transistors are connected in common.
A bias is applied from a voltage source 1116, and a gain control voltage 85 is provided between each base connection point. The collector of transistor 311 and the collectors of transistor No. 6 are each commonly connected. The collector of the transistor 8 is further connected to the terminal of the transistor Km, and the collector of the transistor 6 is further connected to the terminal of the transistor 8. The 80 base, Tungstaff, and 80 base are commonly connected.

Furthermore, it is connected to the collector of transistor 8.

The collector of the transistor 80 is connected to the power supply 56), and the collector of the transistor 80 is connected to the power supply 11 through the resistor S.
35 and to the output terminal 22.

The input signal from the signal source 11 is amplified by the transistor p1 and supplied to the transistor s and the transistor No. 31. Since the current that can flow through the transformer and the transistor No. 31 is controlled by the gain control voltage 26, the transistor 2.Langistor lO
The output signal is distributed accordingly to the transistor 3.4, and the signal via the transistor 1 is obtained via the transistor 8 from the output terminal 2. Therefore, the gain control voltage 26 also controls the gain.

Transis? jl, δ and 6 do not directly contribute to the gain control operation - IIX, these transistors.

It is provided to stabilize the DC voltage when there is no signal. In other words, the collector of transistor 3.5 and the collector of transistor No. 6 are commonly connected, and "')j
Since the bases of transistors 4 and 60 and transistors 3 and 6 are connected in common.

As the current flowing through the transistors 5 and 5 increases, the current flowing through the transistors 5ea and 5 decreases, and as a result, the collector voltages of the transistors 3 and 6 are stabilized.

However, 1. If such a circuit is integrated, the transistor pairs 3 and 4 and the transistor pairs δ and sK characteristics will be packed. Due to this variation, the collector-emitter threshold voltage Van of each transistor is different.
b. The base-to-works voltage V and m, which depend on this, differs and an offset voltage occurs. As a result, an unbalanced state occurs in the circuit, and the stabilization of the output DC voltage deteriorates.

In order to eliminate such drawbacks, in this embodiment, the collectors of transistors B and 6 are connected to the transistors t! of transistors 1.8 and t! 1 wire, and the bases of the transistors 80 and 80 are connected in common, and further connected to the collector of the transistor 8, which has output terminals j1 and ts4. That is, a constant DC voltage obtained across the load resistor aa is supplied to the base of the transistor 1B, and the transistor is turned off.

Since the base-emitter voltage VB is also constant, the collector voltages of transistors 3 to 11i6 are equal. As a result, the voltage 70m between the collectors and terminals of the transistors S to 6 becomes equal by subtracting the bias power supply 160 voltage from the base voltage of the transistor 80), and the offset voltage 4 is reduced, resulting in a high degree of balance. Realized.

By providing a load resistor and an output terminal so that an output can also be obtained from the collector side of the transistor, this output can be used to perform uniform grinding/m*gain control on other circuits.

According to the device 11 as described above, a gain control circuit is provided because it has a high degree of balance.

A simple explanation of aglm Figure 1 is a circuit diagram showing an embodiment of the present invention.

Claims (1)

[Claims] IIl device in which the input signal is supplied to the base? a first emitter write transistor with a bias voltage applied to its base; The collector output of the l1lO industrial ivy grounded lid transistor '0 is supplied to the industrial ivy transistor, and the control voltage is supplied to the base of the &lIr5 transistor and differentially connected to the third transistor ($1140)?
7J, A and 6 transistors, to which the gain control voltage is supplied to the base and whose collectors are connected to the collectors of the 115O) transistors; The collector of the mff1llae Ece data grounded lid transistor is connected to the transistor 9II6, and the collector is differentially connected to the sixth transistor, and the collector is connected to the fourth transistor 0:2 collector.
The transistor 11180) has a transistor connected to its collector and a constant DC bias voltage to its base; 911 whose base is connected to the base of said 〒th transistor;
8 transistors, and means for extracting an output from the collector of at least four of the first and @e transistors 10.