JPS58130595A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS58130595A
JPS58130595A JP1314982A JP1314982A JPS58130595A JP S58130595 A JPS58130595 A JP S58130595A JP 1314982 A JP1314982 A JP 1314982A JP 1314982 A JP1314982 A JP 1314982A JP S58130595 A JPS58130595 A JP S58130595A
Authority
JP
Japan
Prior art keywords
solder
board
circuit board
printed circuit
producing printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1314982A
Other languages
Japanese (ja)
Inventor
邦雄 川口
上山 宏治
小黒 寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP1314982A priority Critical patent/JPS58130595A/en
Publication of JPS58130595A publication Critical patent/JPS58130595A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明a印刷配線収の製造方法、秤しくに、印刷配#板
の装造工程において回路形成俊ソルメーレジスト印刷」
、マスキングチーブ等にエリマスキングさny’cm分
以外、ま九は全面に牛山tコーティングする方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention (a) is a method for producing a printed circuit board, particularly in the manufacturing process of a printed wiring board, and is characterized by "Solmer resist printing"
This is a method of coating Ushiyama T on the entire surface of the masking tube, etc., except for the ny'cm portion of the edge masking.

尻仕−叡に行なわnているスルホール印刷配線板の製造
方法は穴めけ後スルホールを言めて必安な回路形成を行
っている。その後この回路上VCソルダーレジス)t−
印刷1ftは焼付法で付与し%部品実装後の牛田揚は時
に選択的に半田r@上に付与し、S品との朕続、スルホ
ールの信頼性の向上、銅の腐食防止t−なしている0C
(1)ときはんだ揚げ面の鋼表面が酸化汚呆していると
ばんだが充分に鋼上に付与することかT:きず、部品と
の接続、スルホール信頼性、銅の腐食防止か完全でない
。そこで仁の鋼弐圓にめらかじめ半田を付与することに
↓り上記問題を肩決しておりその方法としてはんだめっ
き法とホットエアレベリング法があるが経済性からホッ
トエアレベリング法がiIk近多く使用式tしている@
この方法は回路形成後の印刷配線板にソルダーレジスト
印刷又はマスキングチーブ咎にエリマスキングさt″L
7を部分以外、t7tは全面に早出コーティングする目
的で基板を溶融した半田に凌漬故ホットエアーレベリン
グする方法であ/:lciしかしこの方法は基板を24
0℃前俊の齢も2した半田に浸漬するために基板に急e
liな熱涙化かありξ−ズリング、ふくn等基板に恋影
誓を与えることがおった・この対重として7ラックス慮
布彼轟板をあらかじめ′a融した半田に浸漬する罰に5
0〜100℃の表面TNA度になるようyc予*7JU
熱しその俊浴融した半田に浸漬する方式も一部用いらn
ているか装置的に構造が複雑r(なりメンテナンスかや
りにくい問題が6つ次Q本党明りゴ基板への急撤な熱涙
化にエフ発生するミーズリンダ等の恐影響金防止する目
的″′c?Tう予儒〃口熱方法の改良に関するものであ
る。
The manufacturing method of through-hole printed wiring boards, which is carried out on a regular basis, allows through-holes to be formed after drilling, thereby forming an inexpensive circuit. Then, on this circuit, VC solder resist) t-
1ft of printing is applied by the baking method, and after the parts are mounted, Ushida is sometimes selectively applied on the solder r@, to connect with S products, improve the reliability of through holes, and prevent copper corrosion. There is 0C
(1) When the steel surface of the soldering surface is oxidized and contaminated, it is not possible to apply enough bander to the steel. T: It is not perfect for preventing scratches, connection with parts, through-hole reliability, and corrosion of copper. Therefore, we decided to apply a smooth and damp solder to Jin's steel plate ↓ to solve the above problem, and there are solder plating methods and hot air leveling methods, but the hot air leveling method is often used due to economic efficiency. I am doing @
This method involves printing a solder resist on a printed wiring board after circuit formation or performing edge masking on a masking chip.
t7t is a method of hot air leveling by immersing the board in molten solder for the purpose of quickly coating the entire surface except for the part 7.
Temperature is 0°C.
There were times when I would give a love oath to the board, such as hot tears, ξ-zuring, etc. As a counterweight to this, 7 lacs of cloth was used to punish the board by dipping it in pre-melted solder.
Yc pre-preparation *7JU to achieve surface TNA degree of 0 to 100℃
A method of immersing in hot water and molten solder is also used in some cases.
The device has a complex structure (there are six problems with maintenance and difficulty).The purpose is to prevent the influence of metallurgy, etc., which occurs due to hot tearing when suddenly removed from the main board. ?This relates to improvements in the heat-of-mouth method.

不発91a必賛に応じスルホールt−有す基板に回&を
杉取俊、予じめ短められ次パターンの早出レジストを形
成し、室温以上の高温に保つ友FJIJ処理液に泰板會
浸債恢、溶融牛田に浸漬、ホットエアでレベリングする
ことを%徴とするものである。
In response to the unexploited 91a request, Shun Sugitori fabricated a substrate with through-holes, which was shortened in advance to form a quick-release resist for the next pattern, and immersed the board in FJIJ processing solution, which was kept at a high temperature above room temperature. It is characterized by being immersed in molten clay and leveled with hot air.

丁なわち本発明は半田浸漬前に通常20℃前債の量編q
)72ツクス中に基板を置漬する所を例えは70〜10
0℃に弁部したスラックス中jlc 1秒〜6分閣浸漬
し几たちに例えば220〜260℃の溶融牛田伽中に6
秒〜50抄闇浸漬し次にホットエアー全例えは1■/J
〜6■/−の範囲で吹きつけ半田をレベリングし九飲空
冷するものである。
That is, in the present invention, the amount of solder is usually 20℃ before immersion in solder.
) The place where the board is placed in 72x is 70~10
Soak in slacks for 1 second to 6 minutes at 0°C, and then soak in molten Ushida Gaya at 220 to 260°C for 6 seconds.
The whole analogy is immersion in darkness for 50 seconds and then hot air for 1■/J.
The sprayed solder is leveled in the range of ~6/- and air-cooled for nine times.

以下実施例により本発明をA体的に脱明する。The present invention will be explained in detail by way of Examples below.

実施例 回路形成し次基板を70〜100℃に昇−し7t7ラツ
クス(たとえは水溶性ロジン糸フラックス)中に1秒〜
5分関浸漬し、基板の温度を昇温させた後220〜26
0℃の#I&lした午出槽に浸漬し次に1 kg/7〜
6kg/ばの鍋扇のエアーを吹きつffながら基板を引
き上けることにLり余分な半田を除去しスルホール内シ
゛工ひランド等の鋼上に数ミクロンから数十ゼクロンの
半田をコーティングする・ 不方式に151i!遺した2Ii′aの耐熱性について
評価し次結未t−表−1に示す・ 以上胱明したように不発明に1扛ばスラックスの塗布と
予v4加熱との2つの目的を同時に行うことができ経瞬
性を向上させ、lW1時に基板へqノ最小味にとどめる
ことかできgi軸性を向上さ[Φことができ九〇 すなわち、本発明による製造方法に工r′LF!簡率に
してしかし鮭陽的に従来問題になってい友千田コーティ
ング時にA4!iへの幾影響を解決することかでさ、安
価で信頼性の尚い印刷配#M82r提供丁ゐことかでき
るのであるO 代理人弁理士 若 林 邦 診
After forming the example circuit, the substrate was heated to 70 to 100°C and placed in 7T7 flux (for example, water-soluble rosin thread flux) for 1 second to 100°C.
After dipping for 5 minutes and raising the temperature of the substrate,
Immerse it in a #I&l morning bath at 0°C and then add 1 kg/7~
Remove excess solder by pulling up the board while blowing air from a 6 kg/pan fan, and coat the solder of several microns to several tens of microns on the steel such as the engineering land inside the through hole.・Unformally 151i! The heat resistance of the remaining 2Ii'a was evaluated and the results are shown in Table 1.As explained above, it is possible to uninventively accomplish the two purposes of slack application and preheating at the same time with one stroke. In other words, the manufacturing method according to the present invention improves the instantaneous property and minimizes the amount of q to the substrate during lW1, improving the gi axis property [Φ90]. Although it is simple, it has become a problem in the past when using Tomo Senda coating A4! By solving the impact on i, it is possible to provide inexpensive and reliable printing M82r.O Agent Patent Attorney Kuni Wakabayashi

Claims (1)

【特許請求の範囲】[Claims] 1、 必蒙にもじスルホールを有丁着板に回路を形b)
t、彼、fじめ犀めらILLバター/の半田レジストを
形成し、璽龜以上の高龜に珠りた前処mgK島板t−浸
漬俊、浴−千出に投置、ホットエアでレベリングするこ
とt%倣とする印刷配線板の製造方法・
1. Form the circuit on the board with the through holes attached b)
Form a solder resist of humid ILL butter, put it on a pre-preparation mgK island plate at a height higher than a sill, dip it in the bath, and put it in hot air. A method for manufacturing a printed wiring board using leveling and t% copying.
JP1314982A 1982-01-28 1982-01-28 Method of producing printed circuit board Pending JPS58130595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1314982A JPS58130595A (en) 1982-01-28 1982-01-28 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1314982A JPS58130595A (en) 1982-01-28 1982-01-28 Method of producing printed circuit board

Publications (1)

Publication Number Publication Date
JPS58130595A true JPS58130595A (en) 1983-08-04

Family

ID=11825101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1314982A Pending JPS58130595A (en) 1982-01-28 1982-01-28 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS58130595A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド インコ−ポレ−テツド Printed circuit board manufacturing method
JPS63503585A (en) * 1986-06-18 1988-12-22 マクダーミッド,インコーポレーテッド Improved methods for printed circuit board manufacturing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63500837A (en) * 1985-08-08 1988-03-24 マツクダ−ミツド インコ−ポレ−テツド Printed circuit board manufacturing method
JPS63503585A (en) * 1986-06-18 1988-12-22 マクダーミッド,インコーポレーテッド Improved methods for printed circuit board manufacturing

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