JPS58129737U - solid state delay line - Google Patents

solid state delay line

Info

Publication number
JPS58129737U
JPS58129737U JP19907182U JP19907182U JPS58129737U JP S58129737 U JPS58129737 U JP S58129737U JP 19907182 U JP19907182 U JP 19907182U JP 19907182 U JP19907182 U JP 19907182U JP S58129737 U JPS58129737 U JP S58129737U
Authority
JP
Japan
Prior art keywords
delay line
solid state
state delay
groove
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19907182U
Other languages
Japanese (ja)
Other versions
JPS6121865Y2 (en
Inventor
柳田 ▲あ▼
Original Assignee
昭和電線電纜株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電線電纜株式会社 filed Critical 昭和電線電纜株式会社
Priority to JP19907182U priority Critical patent/JPS58129737U/en
Publication of JPS58129737U publication Critical patent/JPS58129737U/en
Application granted granted Critical
Publication of JPS6121865Y2 publication Critical patent/JPS6121865Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
  • Pulse Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の遅延線の一実施例平面図、第2図は第
1図n−n’線より見た拡大横断面図、 。 第3図及び凹溝6の変形例横断面図、第4図は比較例横
断面図、第5図と第6図はそれぞれ本発明の他の実施例
の領域5部分の拡大平面図及び横断面図で、1は遅延媒
体、2は入カドランスジューサ、3は出カドランスジュ
ーサ、5は主信号継路4以外の領域、6は凹溝、7は凹
部を示す。
FIG. 1 is a plan view of an embodiment of the delay line of the present invention, and FIG. 2 is an enlarged cross-sectional view taken along line nn' in FIG. 1. FIG. 3 is a cross-sectional view of a modified example of the groove 6, FIG. 4 is a cross-sectional view of a comparative example, and FIGS. 5 and 6 are an enlarged plan view and a cross-sectional view of a portion of region 5 of another embodiment of the present invention. In the top view, 1 is a delay medium, 2 is an input current reducer, 3 is an output current reducer, 5 is an area other than the main signal connection path 4, 6 is a groove, and 7 is a recess.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 遅延媒体の主信号継路によって四方を囲まれたほぼ方形
の領域内に、この領域のほぼ中央部に最深部を有し両端
に向ってその深さが滑らかに減少する凹溝もしくは凹部
を設けたことを特徴とする固体遅延線。
A groove or recess is provided within a substantially rectangular region surrounded on all sides by the main signal connection path of the delay medium, with the deepest portion approximately at the center of this region and whose depth decreases smoothly toward both ends. A solid-state delay line.
JP19907182U 1982-12-27 1982-12-27 solid state delay line Granted JPS58129737U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19907182U JPS58129737U (en) 1982-12-27 1982-12-27 solid state delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19907182U JPS58129737U (en) 1982-12-27 1982-12-27 solid state delay line

Publications (2)

Publication Number Publication Date
JPS58129737U true JPS58129737U (en) 1983-09-02
JPS6121865Y2 JPS6121865Y2 (en) 1986-07-01

Family

ID=30112117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19907182U Granted JPS58129737U (en) 1982-12-27 1982-12-27 solid state delay line

Country Status (1)

Country Link
JP (1) JPS58129737U (en)

Also Published As

Publication number Publication date
JPS6121865Y2 (en) 1986-07-01

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