JPS58129725U - Frequency characteristic adjustment circuit - Google Patents

Frequency characteristic adjustment circuit

Info

Publication number
JPS58129725U
JPS58129725U JP1441082U JP1441082U JPS58129725U JP S58129725 U JPS58129725 U JP S58129725U JP 1441082 U JP1441082 U JP 1441082U JP 1441082 U JP1441082 U JP 1441082U JP S58129725 U JPS58129725 U JP S58129725U
Authority
JP
Japan
Prior art keywords
range
adjustment circuit
frequency characteristic
characteristic adjustment
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1441082U
Other languages
Japanese (ja)
Inventor
隆一 福田
藤原　柾美
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP1441082U priority Critical patent/JPS58129725U/en
Publication of JPS58129725U publication Critical patent/JPS58129725U/en
Pending legal-status Critical Current

Links

Landscapes

  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の１実施例を示すブロック図、第２図は
その動作説明図、第３図は本考案の他の実施例を示すブ
ロック図、第４図はその動作説明図である。 図中、２及び４はそれぞれ低域の上昇又は下降回路、又
は高域の上昇又は下降回路である。Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is an explanatory diagram of its operation, Fig. 3 is a block diagram showing another embodiment of the present invention, and Fig. 4 is an explanatory diagram of its operation. . In the figure, numerals 2 and 4 are a low frequency rising or falling circuit, or a high frequency rising or falling circuit, respectively.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 低域又は高域上昇回路と、低域又は高域下降回路とを縦
列に接続し、前記上昇又は下降回路の上昇又は下降周波
数を調整し、総合特性で低域又は高域の周波数特性を調
整することを特徴とする周波数特性調整回路。A low-range or high-range rising circuit and a low-range or high-range falling circuit are connected in series, the rising or falling frequency of the rising or falling circuit is adjusted, and the frequency characteristics of the low or high range are adjusted by the overall characteristic. A frequency characteristic adjustment circuit characterized by:
JP1441082U 1982-02-04 1982-02-04 Frequency characteristic adjustment circuit Pending JPS58129725U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1441082U JPS58129725U (en) 1982-02-04 1982-02-04 Frequency characteristic adjustment circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1441082U JPS58129725U (en) 1982-02-04 1982-02-04 Frequency characteristic adjustment circuit

Publications (1)

Publication Number Publication Date
JPS58129725U true JPS58129725U (en) 1983-09-02

Family

ID=30026881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1441082U Pending JPS58129725U (en) 1982-02-04 1982-02-04 Frequency characteristic adjustment circuit

Country Status (1)

Country Link
JP (1) JPS58129725U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS444352Y1 (en) * 1967-04-14 1969-02-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS444352Y1 (en) * 1967-04-14 1969-02-18

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