JPS58129715U - Input path selection device - Google Patents
Input path selection deviceInfo
- Publication number
- JPS58129715U JPS58129715U JP2726182U JP2726182U JPS58129715U JP S58129715 U JPS58129715 U JP S58129715U JP 2726182 U JP2726182 U JP 2726182U JP 2726182 U JP2726182 U JP 2726182U JP S58129715 U JPS58129715 U JP S58129715U
- Authority
- JP
- Japan
- Prior art keywords
- path selection
- selection device
- input path
- input
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案を適用出来る従来の増幅回路を示す回路
図、第２図は本考案の一実施例を示す回路図、第３図及
び第４図は本考案の動作を説明する線図である。
図中、１３は制御回路、１４．１５及び１６は遅延回路
である。Fig. 1 is a circuit diagram showing a conventional amplifier circuit to which the present invention can be applied, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 are diagrams explaining the operation of the present invention. It is. In the figure, 13 is a control circuit, and 14, 15 and 16 are delay circuits.
Claims (1)
力系路に並列に第３の切換器を接続して第２の入力系路
とし、上記各切換器をオンオフ制御して上記第１又は第
２の入力系路のうちの一方を選択するものにおいて、上
記第１又は第３の切換器のうちの一方を上記第２の切換
器よりも遅らせて動作させる遅延手段を設けることによ
り、上記各切換器が同時のＯＮとなることのない様にし
たことを特徴とする増幅回路の入力糸路選択装置。A third switch is connected in parallel to a first input system in which first and third switches are provided before and after the amplifier to form a second input system, and each of the switches is controlled to turn on and off. In the device for selecting one of the first or second input path, a delay means is provided for operating one of the first or third switching device later than the second switching device. An input yarn path selection device for an amplifier circuit, characterized in that, by doing so, each of the switching devices is prevented from being turned on at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2726182U JPS58129715U (en) | 1982-02-26 | 1982-02-26 | Input path selection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2726182U JPS58129715U (en) | 1982-02-26 | 1982-02-26 | Input path selection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58129715U true JPS58129715U (en) | 1983-09-02 |
Family
ID=30039174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2726182U Pending JPS58129715U (en) | 1982-02-26 | 1982-02-26 | Input path selection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58129715U (en) |
-
1982
- 1982-02-26 JP JP2726182U patent/JPS58129715U/en active Pending
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