JPS58129652A - Floating-point type arithmetic unit - Google Patents

Abstract

PURPOSE:To sharply shorten processing time, by constituting the titled unit so that all processing can be executed within the prescribed processing time of a switching means even if the number of bits to be shifted for normalization and digit justification is large. CONSTITUTION:When mantissas B1, A1 are composed of N-bit data, the titled unit is provided with N-1 input data lines, N-1 code bit lines and output data blocks N1-Nn-1. In the output data block Nn-2, the order of connection is fixed so that the output data bit of the adjacent output data block Nn-1 is shifted only by one bit. In the same manner, respective blocks are connected so as to obtain output data by shifting the input data one bit each successively. When the number of shifted bits is ''1'', the output data block Nn-2 is selected by a control signal and data supplied to the block are outputted as output data after digit justification.

Description

[Detailed Description of the Invention] The present invention relates to an arithmetic unit that performs addition and subtraction of numerical values in floating-point format, and in particular to an arithmetic unit that is designed to significantly reduce the processing time for digit alignment and normalization of the mantissa part compared to conventional methods. It is.

A.8 Addition and subtraction processing of two numerical values in floating point format has conventionally been carried out using the following procedure.90 First, numerical values A and B are represented by a mantissa part and an exponent part as follows.

A-A 1 rice 2Ac1・・・・・・(11B=B
l rice 2 ・・・・・・・・・(2) First, compare the exponent parts Ae and Be to determine the size of the exponent part,
In this example, the other exponent part is set to match the larger exponent part. Therefore, when Ae≧Be, #/c sets the exponent part of the operation result to temporary KAe, and the mantissa part Bl of the numerical value B.
is shifted to the right by Ae-Be bits, and the same sign bit (MSB) of B1 is inserted from the left to perform digit alignment.

The new mantissa part Bl obtained by this digit alignment operation
' and A1 are added and subtracted, and if the result is not in a predetermined format, the result is normalized. For normalization, the calculation result is shifted appropriately, and the exponent part is changed accordingly and changed into a round format.

Such digit alignment and normalization operations have conventionally been performed using a shift register or the like. Therefore, when the number of bit shifts for digit alignment or the number of bit shifts for rounding for normalization is large, there is a drawback that processing time for digit alignment and normalization processing time is long.

Therefore, in the present invention, even if the bit shift amount for normalization and digit alignment rounding is large, it can all be processed within the unit processing time of the switching means. Next, an example of the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

First, for convenience of explanation, it is assumed that the mantissa parts AI and Bl are expressed in binary numbers, and the exponent parts Ae and Be are respectively expressed in decimal numbers. The numerical values A and B are tentatively expressed as follows.

B 1 =00110100 Be=3
(4) - As an example, in FIG. 1, which describes the subtraction processing operation, the exponent parts Ae and Be are supplied to the exponent part comparison block QIK, and the exponent parts Ae and Be are compared. The output controls the branching state of the mantissa AI and 81 supplied to the branch block (2Q).In this example, the larger exponent part is matched with the smaller exponent part, so the smaller exponent part is Branching is controlled so that the mantissa belonging to the digit alignment block (to) is supplied to the digit alignment block (to).For example, when numerical values A and B are expressed as in equations (31 and (4)), B e (Since A e, supply it to the mantissa part B1ft digit alignment block (to) and make Ae-Be
Shift the mantissa part B1 by a bit. Along with this bit shift, the same part as the mantissa part B10M5B is filled from the left. Therefore, the new mantissa part Bl' with digits aligned is as follows.

B1'=00011010...
(5) This digit alignment operation of the mantissa part B1 is performed simultaneously by a digit alignment block (1) as shown in FIG.

When the mantissa part Bl and AI are composed of N-bit data, N-1 input data lines are provided, and N-1 sign bit lines are provided, and the sign bit line contains the mantissa. The sign bit of part A1 or B1 is commonly supplied. n output data blocks N1% for these input data lines and code bit lines
Nn-1 is provided.

Each block KFiN output data lines are provided, and the input data lines and symbols are arranged such that from block Nn-1 no data bits are shifted, i.e. the data of seven input data pits are obtained as output bits. The bit line and the output data line are connected. Therefore, the input data line of the LSB bit is connected to the output data line of the L8B bit, and the sign bit line is directly connected to the output side sign bit line (MSB).

On the other hand, output data block Nn-! In,
The wiring order is determined so that the output data bits of the adjacent output data line Nn-1 are shifted by one bit. Therefore, the output data line of the LSB bit is L8.
Connected to the input data fin of bit B + 1.
Of these output data lines, the MOB bit output data line and the MSB-1 bit output data line are respectively connected to the code bit line.

Thereafter, in the same manner, each book is sequentially shifted one bit at a time and wired so that the incoming data is obtained as the output data.

However, since the number of bit shifts required for digit alignment is N-1 bits, the output data line of L8B bits of the first block N1 is connected to the input data line of MSB-1 bits.

# for each of these N-1 plurality of output data blocks
- Switching means 81 to 8 l as shown in Figure 1 are provided, one output data block is selected by the control signal supplied to these, and the mantissa part in which the data from the selected output data block is digit-aligned. This becomes the data of Bl.

Therefore, if there is one shift bit as described above,
The control signal selects the output data block Nn-, and the data supplied to this block is output as output data after digit alignment.

If Ae-Be=N-2, the output data block N2 is selected and the data shifted by N-2 bits is output as the data of the mantissa part B1'.

Note that three-state switching elements or the like can be used for the above-mentioned switching means Sl to Sn.

Furthermore, the control signal formed by the exponent comparison block OI is used. That is, this block Ql
In the step, the exponent parts Ae and Be are compared, and a control signal corresponding to the magnitude thereof is generated.

The mantissa part Bl/k after digit alignment is supplied to the arithmetic circuit (ALLJ) along with the mantissa part AI obtained from the other branch block, and the mantissa part AI and Bl' are subtracted. Let the result be C1. This subtraction output C1 is supplied to the normalization block group. The normalization block (to) determines the input mantissa part C1 so that the mantissa part CI is in the specified format, and if it is not in the specified format, This is a block for obtaining exponent part changing data that performs bit shifting to an appropriate value according to the data content and changes the exponent part accordingly. In this example, the MSB bit and the MSB
-1 bit are equal, and MSB-1 bit and MSB-
It is assumed that the format is determined so that two bits are different.

As shown in FIG. 3, the normalization block is provided with N input data lines according to the number of data in the mantissa part C1, and N-2 data lines for bit shifting. All data lines of are grounded and N+1 output data blocks N, including the block for protect bit correction; 5-pJn
t is provided. Each of these blocks has N output data lines, and these N output data lines, N input data lines, and N-2 bit shifting data lines are shown in FIG. are connected in the same way as.

Output data block N. ' is a block for protecting bit correction @ Therefore, the output data line of MSB bit and the output data line of MSB-1 bit are MSB
Connected to the bit's input data line. The next output data block Nl/ is the output data block when no normalization is required, so its output data lines are connected to only N input data lines.

On the other hand, the third block N2' is a case where normalization is required and normalization with a 1-bit shift is required, and among the output data lines, the output data line of the MSB bit is the input data line of the MSB bit. The output data line of the MSB-1 bit is connected to the input data line of the MSB-2 bit, and then the output data line and the input data line are connected so as to shift one bit at a time, and then the output data line of the MSB-1 bit is connected to the input data line of the MSB-2 bit. The output data line of is connected to one of the bit shifting data lines.

Then, the last output data block Nn/ is its MS
The output data line of the B bit is connected to the input data line of the M8B bit, and all the output data lines below the MSB-s pit are connected to the data line for bit shifting. Therefore, in the above example, Mantissa part ciFi output from λLU-, CI=AI-Bl'-00010010...
Since the data is as shown in (6), the normalization is the same in this case, so in this example, normalization is performed by a 1-bit shift. The data after normalization is shown as (712).

CI'=00100100 ・・・・・・・・・
...(7) Therefore, in the normalization block, the third
Only the switching means 86' provided in the output data block turns on, and the nine switching means provided in the other output data blocks R86s8t *
8'z+... A control signal that turns off all S6 may be supplied.

A control signal is provided on the input data line and is formed by decoding the data in the nine mantissa C1. 5υ is a decoder for that purpose. For example, if the output data pit of the mantissa CI is as shown in equation (8), it is necessary to normalize it as shown in equation (9). A control signal is generated such that the data is output.

ct=ooooooooi ・・・・・・・・・
・・・(8) CI'=00100000 ・
(9) It is necessary to change the exponent part by normalizing the mantissa part in this way. Therefore, in this example, the data of the mantissa part C1 supplied to the input data line is further supplied to the decoder@, and it is detected by how much the exponent part needs to be changed. Therefore, this normalization block - outputs the normalized mantissa (called C1') and exponent change data to change the exponent. The larger exponent part output from block 01, in this example exponent part A6
is supplied, and at the same time, the modified data of the exponent part output from the normalization block (to) is supplied and subtraction is performed.

For example, for the exponent part ke = 4 assumed above, the mantissa part C1 is normalized and rounded by shifting it by 1 bit, and the exponent part is changed from 4 to 3. 0 Let's find the output of this block l. This is the exponent part Ce of the subtracted output.

On the other hand, the normalized mantissa CI' output from the normalization block and the branch block c! AL branched at I
The mantissa supplied to U-, dAl in this example, is supplied to the Oshima multiplex tmVcm, and the selection of A1 or 01' is performed. This multiplex? In (to), if the difference in the exponent parts is small, the normalized mantissa part CI' is output, but if the difference in the exponent parts is too large, the mantissa part A1 is output as is. This multiplexer is controlled by the output pressure of the exponent comparison block member.

As a result of the above arithmetic processing, the mantissa part CI' or A of the subtraction output to be obtained from the multiplexer (to) is
1 is output, and the final exponent part Ce is output from the exponent part changing block -.

As explained above, in this invention, shift registers etc. are not used for digit alignment and normalization, so
An operation equivalent to the multiple pit shift operations required for data alignment and normalization can be performed by selecting one block.

Therefore, the processing time required for data digit alignment and normalization is the unit switching time of the switching element provided in the switching means 8x-8n-x r 8'o-86, so the processing time is significantly reduced compared to the conventional method. can do.

Note that in all of the above embodiments, the relationship between each block and the input data line was explained when the mantissa was expressed in two's complement format; however, the mantissa was expressed in unsigned format. The present invention can also be applied to such cases.

[Brief explanation of drawings]

Fig. 1 is a system diagram showing an example of the main parts of a floating-point arithmetic unit according to the present invention, Fig. 2 is a connection diagram showing an example of a digit alignment block, and Fig. 3 is a connection diagram showing an example of a normalization block. It is a diagram. 0I is the exponent comparison block, (to) is the digit alignment block (
41#1ALU% ω is a normalization block, Il is an exponent changing block, and (to) is a multiplexer. Agent Yumi Ise

Claims (1)

[Claims] In a floating-point format arithmetic unit, an output data block that outputs the same data as the input data of the mantissa part;
It has a plurality of output data blocks in which data obtained by shifting the above input data by 1 bit is output, and thereafter a plurality of data with different data contents obtained by sequentially shifting the above input data by 1 bit are output, and the bit shift of the mantissa part is performed. A floating point format % expression % with a button that selects one of the plurality of output data blocks according to the amount and outputs the mantissa data bit-shifted by a predetermined amount.