JPS58127732U - oscillation circuit - Google Patents

oscillation circuit

Info

Publication number
JPS58127732U
JPS58127732U JP2311682U JP2311682U JPS58127732U JP S58127732 U JPS58127732 U JP S58127732U JP 2311682 U JP2311682 U JP 2311682U JP 2311682 U JP2311682 U JP 2311682U JP S58127732 U JPS58127732 U JP S58127732U
Authority
JP
Japan
Prior art keywords
transistor
reference voltage
current
oscillation circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2311682U
Other languages
Japanese (ja)
Inventor
文彦 横川
洋一 小川
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP2311682U priority Critical patent/JPS58127732U/en
Publication of JPS58127732U publication Critical patent/JPS58127732U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は発振回路の従来例を示すブロック図、第2図は
本考案の発振回路の実施例を示す回路図、第3図は第2
図の回路の動作波形図、第4図は第  。 2図の回路の具体回路図である。゛ 主要部分の符号の説明、1,7・・・・・・積分回路、
2.3・・・・・・比較回路、4・・・・・・フリップ
フロップ、5.6・・・・・・カレントミラー回路。 第1図 第2図
Fig. 1 is a block diagram showing a conventional example of an oscillation circuit, Fig. 2 is a circuit diagram showing an embodiment of the oscillation circuit of the present invention, and Fig. 3 is a block diagram showing a conventional example of an oscillation circuit.
The operating waveform diagram of the circuit shown in Fig. 4 is shown in Fig. 4. FIG. 2 is a specific circuit diagram of the circuit shown in FIG. 2;゛Explanation of symbols of main parts, 1, 7...Integrator circuit,
2.3...Comparison circuit, 4...Flip-flop, 5.6...Current mirror circuit. Figure 1 Figure 2

Claims (4)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)  入力電流に応じて出力電圧が増減する電圧可
変手段と、所定の異なる2つの基準電圧のうちの一方を
選択的に発生する基準電圧発生手段と、前記電圧可変手
段の出力電圧がその入力に供給される第1のトランジス
タと前記基準電圧発生手段の基準電圧がその入力に供給
され前記第1のトランジスタと差動接続された第2のト
ランジスタとを有する比較手段と、前記第1のトランジ
スタのオン・オフに対応して前記電圧可変手段の入力電
流を制御する第1の電流供給手段と、前記第2のトラン
ジスタのオン・オフに対応して前記基準電圧発生手段の
基準電圧を制御する第2の電流供給手段とを備えること
を特徴とする発振回路。
(1) Voltage variable means whose output voltage increases or decreases depending on the input current, reference voltage generation means which selectively generates one of two predetermined different reference voltages, and an output voltage of the voltage variable means that a comparing means having a first transistor supplied to an input; and a second transistor having an input supplied with the reference voltage of the reference voltage generating means and differentially connected to the first transistor; a first current supply means for controlling the input current of the voltage variable means in response to on/off of the transistor; and a reference voltage for the reference voltage generation means in response to on/off of the second transistor; An oscillation circuit comprising a second current supply means.
(2)前記第1及び第2の電流供給手段は各々カレント
ミラー回路を含むことを特徴とする実用新案登録請求の
範囲第1項記載の発振回路。
(2) The oscillation circuit according to claim 1, wherein the first and second current supply means each include a current mirror circuit.
(3)前記第1の電流供給手段は、そのカレントミラー
回路のオフセット電流を補償する電極を前記第1のトラ
ンジスタに供給する手段を含むことを特徴とする実用新
案登録請求の範囲第2項記載の発振回路。
(3) The first current supply means includes means for supplying the first transistor with an electrode that compensates for the offset current of the current mirror circuit. oscillation circuit.
(4)前記基準電圧発生手段は、ベースに所定電圧が印
加され前記第2の電流供給手段の出力により相互にオン
・オフするプッシュプル接続されたPNP トランジス
タとNPN )ランジスタとを含むことを特徴とする実
用新案登録請求の範囲第1項、第2項又は第3項記載の
発振回路。
(4) The reference voltage generating means includes a push-pull connected PNP transistor and an NPN transistor to which a predetermined voltage is applied to the base and which are mutually turned on and off by the output of the second current supply means. An oscillation circuit according to claim 1, 2, or 3 of the utility model registration claim.
JP2311682U 1982-02-20 1982-02-20 oscillation circuit Pending JPS58127732U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2311682U JPS58127732U (en) 1982-02-20 1982-02-20 oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2311682U JPS58127732U (en) 1982-02-20 1982-02-20 oscillation circuit

Publications (1)

Publication Number Publication Date
JPS58127732U true JPS58127732U (en) 1983-08-30

Family

ID=30035168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2311682U Pending JPS58127732U (en) 1982-02-20 1982-02-20 oscillation circuit

Country Status (1)

Country Link
JP (1) JPS58127732U (en)

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