JPS58127171A - Level indicator - Google Patents

Abstract

PURPOSE:To achieve an automatic flashing at a level near 0dB such as (0dB+ or - 0.1dB) pertaining to a level indicator designed to indicate several levels with individual display segments arranged in a row. CONSTITUTION:Outputs of output terminals t1-t15 of a decoder 12 are fed separately to each one of NOR gates 131-1315. Outputs of an upper level of NOR gates 132-1315 and an output of an upper level of an output terminal t16 are applied to other input terminals thereof 131-1315 while sixteen LEDs D1-D16 are inserted between the NOR gates 131-1315 and the output terminal t16 and a power source terminal 14. Such an arrangement of feeding output signals of an upper level to the NOR gates enables a bar graph indication. A level comparator 9 compares current data with the data preceding by 1 clock stored in an FF10 and when the current data is larger, it is selected with a multiplexer 8. This enables invariable outputting of the max. level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level display device in which a plurality of display segments are arranged in a line and each display segment displays a plurality of levels.

Level display devices are already known that display the peak level of an audio signal or the like in the form of a bar graph or dot graph using display segments such as light emitting diodes, liquid crystals, plasma, etc. However, this level display device
Since the level can only be read in steps of a few dB,
It could not be used in commercial equipment that required accurate input level calibration or gain calibration. Therefore, as shown in Figure 1A, for example -4tOdB in steps of /~ several dB.
Display each level between ~+, 2 Q dB/6
One main display consisting of several light emitting diodes and Q
The range from -0.3 dB to +9.3 dB near dB is set to 0.
/llB step display unit 1B is provided,
Currently, only the area around Q dB is enlarged and displayed.

In this case, as shown in FIG. 1B, the configuration was such that two meter circuits and 2B were provided to generate display signals for one display and 1B.

The configuration shown in FIG. 1 has the disadvantage that the number of display segments such as light emitting diodes increases, and therefore the number of drivers for the display segments also increases, and the area occupied by the display in the panel is large. When a level indicator is provided for each channel as in a multi-channel Teso recorder, a problem arises. Furthermore, the specific level (0 dB in the case of Figure 1 A) that is enlarged
), which had the disadvantage that the user could not use other absolute reference levels.

An object of the present invention is to realize a level display device in which these problems are solved. In other words, this invention,
For example, if a display segment that displays θdB is (θdB
It is designed to automatically blink at a level near θdB, such as ±θ, /aB).

An embodiment in which the present invention is applied to an audio PCM tape recorder will be described below. FIG.
The configuration of that/channel is shown.

The PCM data of bits recorded or reproduced by the audio PCM tape recorder is supplied to the absolute value extraction circuit 3. The PCM data is, for example, J complementary code, and the absolute value extraction circuit 3
For example, when OB is /', all bits are inverted. Strictly speaking, it is necessary to add +/ to the inverted version, but since this is an error in the LSB of the /B bits, this can be ignored. In analog terms, extracting the absolute value corresponds to full-wave rectification. The output data of the absolute value extracting circuit 3 is supplied to level encoders 4 and 5 made up of combinational circuits such as PLA, and davit display data appears from each level encoder 4 and 5. This level encoder 4 and 5
The output of is supplied to multiplexer 6. This multiplexer 6 alternately outputs the outputs of the level encoders 4 and 5 from a terminal 7 in accordance with the (7)/f pulse signal.

The output of this multiplexer 6 is supplied to a multiplexer 8 and a level comparator 9. This multiplexer 8 is
Controlled by the comparison output of the level comparator 9;1. Its output is fed to a seven-bit flip-flop 10. The output of this flip-flop 10 is supplied to a subtracter 11 and a decoder 12. The decoder 12 has a davit of /6
Any seven of its 76 output terminals t1 to tzs will be at a low level ('0'), corresponding to the davit code. Here, tl
It is the output terminal with the lowest level, which is 1θ゜ in the case of 000, and the output terminal with the highest level, which is 1θ' in the case of ·t, 1a, ////. Each output of the output terminals t1 to '15 of this decoder 12 is the NOR gate 1f to '13.
．． 5 is supplied to one input terminal of each of the input terminals. This NOR
Gate 13. The other input terminal of each of ~1315 is
The outputs of N0f (gates 13 to 131.) and the output terminal t16 are added, and 76 light emitting diodes D1 to Dla are connected between the NOR gates 131 to 131□ and the output terminal tt6 and the power supply terminal 14. In this way, a bar graph display can be performed by using a configuration in which the output signal of the upper level is supplied through the NOROR gate.For example, if the davit data is
//, only the output terminal t18 of the decoder 12 is 1
When it comes to θI, all NOR games) 13ta, 131
．． When the output of 13 becomes 1θ', all of the light emitting diodes D1 to I)ta emit light.

Further, the lowest level output signal appearing from the NOR gate 13□ is supplied to the AND gate 15. A decay pulse is supplied to this AND gate 15 from a terminal 16. This decay pulse has a predetermined period of ′/′
The subtracter 11 is controlled by the output of the AND gate 15.

When the output of the AND gate 15 is %OI, the subtracter 11 simply passes the output of the flip-flop 10 and supplies it to the level comparator 9. On the other hand, when the output of the AND gate 15 is '''/# , a subtracter 11 performs the operation of subtracting / from the output of the flip-flop 10. Also, a level comparator 9 compares the current data with the data stored in the flip-flop 10 before the / clock. If the current data is larger, the multiplexer 8 selects the current data.
The multiplexer 8, level comparator 9, and flip-flop 10 always output data at the maximum level, like peak detection. The subtracter 11 is used to reduce the value of the flip-flop 10 by a decay pulse of an appropriate period, like discharging the charge of a capacitor, and supply the reduced value to the level comparator 9. This decay operation is not performed when the data is at the lowest level (0000).

Now, level encoders 4 and 5 are audio, t P
The CM data is compared with a threshold level corresponding to the display level and converted into l-bit data. FIG. 3A shows a level indicator of this embodiment,
As mentioned above, the /6 driven light emitting diodes D1 to D16 are arranged in a straight line in the vertical direction. By these light emitting diodes D1 to D, the minimum level L
Each level is displayed from 1 to the maximum level L16. Specifically, as shown in the figure, (Ll-1ω), (L2=-3+
dB)・・・・・・・・・・・・・・・(Le-/
dB) + (Llo - OdB) (Ll - 10/dB)
. . . (Ll8−10 θaB) is displayed. And level encoder 4
Then, as shown in FIG. 3B, the input data Th'rHt~
It is converted into l-bit data by comparing the threshold level of TH15. For example, the threshold level TH is represented by a level code corresponding to (θdB+/dB). In the output of the absolute value extraction circuit 3, the MSB is always set to 10'.
Since the S bit code appears, the threshold level TH.

is also represented by the /S bit code. Actually, in order to simplify the circuit, the level comparison between the input data and the threshold level is performed while ignoring the lower /~3 pF. Then, the input data is higher than the example 1f threshold level TH9, and for example (/ dB + θ, /
dB), the level encoder 4 to 100/l is smaller than the threshold level TH1o corresponding to
Bit data is output. This 1-bit data causes the light emitting diode DlxDlo to emit light.

The other level encoder 5 also has the same configuration as the level encoder 4, and is configured to compare the input data with each of the threshold levels TL1 to TL1 as shown in FIG. 3C.

Here, as is clear from FIGS. 3B and 3C, the threshold levels TH5 to TH1a of the level encoder 4 are
Each of the threshold levels TL5 to TL15 of the level encoder 5 is made smaller by an amount corresponding to, for example, Q, . - For example, the threshold level TL, is (Q dB - Q, / dB)
It is considered to be equivalent to Therefore, data at levels within the range shown by the hatched area in FIG. In the above example, input data in the range (Q dB±/dB) will generate an output code of 7000 from level encoder 4 and an output code of 10O/dB from level encoder 5.
generates an output code of These two output codes are taken out alternately in the multiplexer 6 and used to drive the light emitting diode, so that the light emitting diode D0° blinks as shown in Figure BK. The period of this blinking is determined by the terminal l for multiplexer 6.
It is determined by the period of the pulse signal supplied from.

If the input data is smaller than (θdB -0, / aB) and exceeds the threshold level TH8, the outputs of level encoders 4 and 5 will both be 100θ, and the light will emit light as shown in Figure A. Diode D9
emits light and Dlo remains off. On the contrary, the input data is (Q aB+ 0./dB) < and the threshold level TLt.

If smaller, the outputs of level encoders 4 and 5 are
Both of them are 100/, and the light emitting diode DIO continues to emit light as shown in Figure C. therefore,
By blinking the light emitting diode DIO, it can be known that the level of the input data is (Q dB 10, / dB). Of course, other light emitting diodes D6n D7.
D81 D91 Dll......The flashing Dla also indicates the level, for example 10, / d.
It is displayed that it is within the range of B.

Also, all 75 bits of the input data except the MSB are '/
' means l Q dB, so the threshold levels TH, J of the level encoder 4 and the threshold levels TL, 6 of the level encoder 5 are, for example, ,/a
B) and (20aB-0, 3aB). Furthermore, since (10,/dB) is a value corresponding to about 7% of the center level, it becomes difficult to form a code having a difference corresponding to ±0.7 dB in a region where the level is too small. Such a difference can be represented by using a larger number of bits, but this increases the circuit scale. Therefore, in this embodiment, up to the light emitting diode D6 can blink.

Note that the value of /dB is - for example, 0.2 dB
θ such as B may be several dB, and the level range of blinking may be changed depending on the value of the center level.

As understood from the above description of the embodiment, the present invention enables high-resolution level display without increasing the number of display segments. Therefore, the space required for the display is small, the number of drivers etc. can be reduced, and only seven meter circuits are required, making it particularly suitable for use in multi-channel level display. Also,
There is an advantage that a plurality of values including θdB can be used as the absolute reference level when performing level calibration by supplying a reference signal during recording, level calibration with a mixer, etc. Further, as in the above-mentioned embodiment, 11-12...... decoder.

The configuration is suitable for devices that handle digital data, and level comparison is not affected by temperature drift or the like, making it stable.

Note that the absolute value extraction circuit 3 may not be particularly provided. Further, the level encoders 4 and 5, the multiplexer 6, and in some cases, the absolute value extraction circuit 3 may be realized by ROM, and in that case, the pulse signal controlling the multiplexer 6 is set as the / bit of the address of ft0M. used. Further, the level display is not limited to a linear level display, but a circular level display or the like may be used.

[Brief explanation of the drawing]

FIG. 1 is a route map and block diagram used to explain a conventional level display device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3, 3, and S are an embodiment of the present invention. It is a route map used to explain the operation of an example. D1-D16 ...... Light emitting diode, 4
, 5... Song interval/level encoder, multiplexer for 6.8 beats..., 12- Agent Masatomo Sugiura Procedural Amendment (voluntary) 1980 16 "Pa° Month 250" Commissioner of the Patent Office Kazuo Wakasugi 1 Display of the case Patent Application No. 10318 of 1982 2 Name of the invention "Level display device" 3 Person making the amendment Relationship with the case Patent applicant 4, agent 6, number of inventions increased by amendment 7, amendment Contents of amendments to the Detailed Description of the Invention column and Drawing 8 in the subject specification + 11 In the specification, on page 3, line 20, "full-wave rectification" is corrected to "after-wave rectification". (2) Same, page 5, line 1, page 5, line 3, page 5, line 4, page 5, line 6. On page 5, line 9, page 5, line 13, and page 5, line 16, "NoR" is corrected to "AND". (3) In the drawings, Figures 2 and 5 will be corrected as shown in the attached drawings.

Claims (1)

[Claims] In a level display device in which a plurality of display segments are lined up and each display segment displays a plurality of levels, a level in which a display segment is automatically flashed at a level in the vicinity of the level indicated by a certain display segment. Display device.