JPS58121671A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58121671A
JPS58121671A JP379782A JP379782A JPS58121671A JP S58121671 A JPS58121671 A JP S58121671A JP 379782 A JP379782 A JP 379782A JP 379782 A JP379782 A JP 379782A JP S58121671 A JPS58121671 A JP S58121671A
Authority
JP
Japan
Prior art keywords
transistor
emitter
base
layer
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP379782A
Other languages
Japanese (ja)
Inventor
Masahiko Aoki
雅彦 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP379782A priority Critical patent/JPS58121671A/en
Publication of JPS58121671A publication Critical patent/JPS58121671A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • H01L29/0813Non-interconnected multi-emitter structures

Abstract

PURPOSE:To reduce Ic (collector current) dependability of hFE by dividing a transistor into numerous number more than two and automatically increasing the number of the transistors which sequentially operate in response to the level of Ic. CONSTITUTION:After collector layers 11, 12 and a base layer 13 are formed, an emitter layer is divided into two regions, and the first and second emitter layers 18, 14 are formed by selectively diffusing doner impurity for auxiliary and main transistors Q1 and Q2. Then, auxiliary transistor Q1 and main transistor Q2 ae shortcircuited at the collectors and emitters with common electrodes by depositing collector electrodes 15, emitter electrodes 16 and base electrodes 17, the transistor Q1 is simultaneously disposed between the base electrode and the transistor Q2, and an insulating film 19 is formed to prevent the base layer 13 from shortcircuiting to the emitter electrode 16.

Description

【発明の詳細な説明】 本発明は半導体装置に係シ、特に電流増巾率11FIi
!のコレクタ電流1c依存性を少くしたトランジスタに
関する〇 一般にトランジスタの重畳な電気特性であるエミッタ接
地電流増巾率hrz (以下単に電流増巾率又はり、五
と呼称する)は;レクタ電流1cに大きく依存する性質
を有してお少、実使用上に於てlcのレベルに応じてペ
ース電流l!1を制御しなければならない欠点を有して
いる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having a current amplification rate of 11FIi.
! Concerning a transistor with reduced dependence on collector current 1c 〇 In general, the common emitter current amplification rate hrz (hereinafter simply referred to as current amplification rate or 5), which is a superimposed electrical characteristic of a transistor, is; Due to its dependent nature, the pace current l depends on the level of lc in actual use! It has the disadvantage that 1 must be controlled.

本発明の目的はかかる欠点を改善し、hp”gのic依
存性を少くしたトランジスタを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to improve such drawbacks and provide a transistor in which the dependence of hp''g on IC is reduced.

本発明の特徴は、−導電型半導体基板の一生面側に一導
電型不純物が拡散されてコレクタ層が形成され、他主面
側に逆導電型不純物が拡散されてベース層が形成され、
該ベース層内に一導電型不純物が拡散されてエミツタ層
が形成された半導体装置において、前記ベース層内にそ
の平面形状が前記エミツタ層をとル囲む如く形成された
一導電型不純物領域が設けられている半導体装置にある
The features of the present invention are as follows: - An impurity of one conductivity type is diffused on one main surface side of a conductivity type semiconductor substrate to form a collector layer, and an impurity of opposite conductivity type is diffused on the other main surface side to form a base layer.
In a semiconductor device in which an emitter layer is formed by diffusing impurities of one conductivity type into the base layer, an impurity region of one conductivity type is provided in the base layer so that its planar shape completely surrounds the emitter layer. It is found in semiconductor devices that are

そして、このような構成によって半導体基板に複数個の
トランジスタを形成し、該トランジスタ絋共通のコレク
タ電極と共通のエミッタ電極を有し、かつひとつの主ト
ランジスタと多数個の補助トランジスタと成し、該補助
トランジスタ祉ベース電極と前記主トランジスタの間に
配置された構造を有する半導体装置とするのである。す
なわち、本発明の特徴は、トランジスタを2ヶ以上の多
数個に分割し、lcのレベルに応じて順次動作するトラ
ンジスタの数を自動的に増加させることにより、hFE
のlc依存性を低減させることにある。
With such a configuration, a plurality of transistors are formed on a semiconductor substrate, and each of the transistors has a common collector electrode and a common emitter electrode, and constitutes one main transistor and a large number of auxiliary transistors. The semiconductor device has a structure in which the auxiliary transistor is disposed between the base electrode and the main transistor. That is, the feature of the present invention is that the hFE is
The objective is to reduce the lc dependence of

本発明に依れば、 lc依存性の少ない平坦なhF。According to the present invention, flat hF with less lc dependence.

特性を有するトランジスタを実現することができる0 次に図面を参照して本発明について説明すると、第1図
(aJ〜(dlは従来のトランジスタの例であって<a
r図はエミッタ側から見たパターンの平面図、(b)図
はA−A’部分のチップ断面図、(C)図は等価回路、
(dJ図はhFEのlc依存性を示す一般例である。こ
のトランジスタはへ型半導体基板1の一方からドナー不
純物を高濃度に拡散してN+層即ちコレクタ層2を形成
し、他方の面からアクセプタ不純物を拡散して1層即ら
ベース層3を形成した後、ドナー不純物を所望の部分に
選択的に拡散して、へ1層即ちエミツタ層4と、核エミ
ッタ層4を取〕囲んで表面に無用した他のベース部分を
形成させ、しかる稜にコレクタC@に金属電極5を、エ
ミッタE側に金属電極6を、ベース露出部5に金輌電極
7を蒸着することによシ、製作される。この様にして製
作されたトランジスタは一般に等価回路(cJ図で示さ
れ、その電流増巾率hFEはコレクタ電流1cに対して
強い依存性を示す。lcが/JSさい領域ではベース−
エミッタ間の接合の表面近傍に於てキャリアの再結合機
構が支配的になり hyEを低下させ、lcが大きい領
域ではベース層内に注入されたキャリア(正孔)密度が
増加するに伴って、電気的中性条件が保たれなくなシ、
これを中和するためにペース電子から電子が供給され、
ペース層内の電子密度も寓くなってエミッタ接合の注入
効率を低下させるため、hFEが低下する現象は従来か
らよく知られているO hFIのlcに依存する程度は
、トランジスタの構造や定格容量等によって異なるが例
えば1c=50A、VCE(SVS)=500V定格の
ダーリントン接続型の大容量トランジスタの例では、l
 c =IA テh、、=soo 、 IC=25Aで
11rF、=a4001c=5OAテbFg=L300
.1c=10OAテh、E=27と著しく変化する。こ
の様なトランジスタをスイッチング用途に供する場合、
 lcに応じてベース電流を可変制御すると同時に、個
々のトランジスタでhFE W性が異なるので全てのト
ランジスタについてベース電流を調整する必要があった
Next, the present invention will be explained with reference to the drawings.
Figure r is a plan view of the pattern seen from the emitter side, Figure (b) is a cross-sectional view of the chip along the line A-A', Figure (C) is an equivalent circuit,
(The dJ diagram is a general example showing the lc dependence of hFE. This transistor is made by diffusing donor impurities at a high concentration from one side of a hemispherical semiconductor substrate 1 to form an N+ layer, that is, a collector layer 2, and from the other side. After the acceptor impurity is diffused to form one layer, that is, the base layer 3, donor impurities are selectively diffused into a desired portion to surround the first layer, that is, the emitter layer 4, and the core emitter layer 4. By forming another unnecessary base part on the surface, and depositing a metal electrode 5 on the collector C@ side, a metal electrode 6 on the emitter E side, and a gold electrode 7 on the exposed base part 5 on the corresponding edge, The transistor manufactured in this way is generally shown in an equivalent circuit (cJ diagram), and its current amplification factor hFE shows a strong dependence on the collector current 1c. In the region where lc is small /JS, the base −
The recombination mechanism of carriers becomes dominant near the surface of the junction between emitters, lowering hyE, and as the density of carriers (holes) injected into the base layer increases in the region where lc is large, Electrical neutrality condition is no longer maintained,
To neutralize this, electrons are supplied from pace electrons,
The electron density in the spacer layer also decreases, reducing the injection efficiency of the emitter junction, so the phenomenon that hFE decreases is a well-known phenomenon. For example, in the case of a Darlington connection type large capacity transistor with a rating of 1c = 50A and VCE (SVS) = 500V,
c=IAteh,,=soo, IC=11rF at 25A,=a4001c=5OAtebFg=L300
.. 1c=10OAteh, E=27, which changes significantly. When using such a transistor for switching purposes,
It was necessary to variably control the base current according to lc, and at the same time to adjust the base current for all transistors since the hFEW characteristics differ between individual transistors.

次に本発明実施例になるトランジスタを第2図(栃〜(
d)を参照しながら説明すると、従来と同様の方法でコ
レクタ層11、及び12、ベース層13を形成した後、
エミツタ層を2つの領域に分割形成させて第1のエミツ
タ層18及び第2のエミツタ層14をドナー不純物の選
択拡散によって形成し、それぞれ補助トランジスタ部Q
、と主トランジスタ部Q!と成し、しかる後にコレクタ
電極15、エミッタ電極16、ベース電極17を蒸着す
ることによって補助トランジスタQ、と主トランジスタ
qはコレクタ及びエミッタを共通の電極で短絡すると同
時に、補助トランジスタQ1をベース電極と主トランジ
スタqの間に配置し、ベース層13がエミッタ電極16
に短絡するのを防ぐために絶縁膜19を設けることによ
って製作される。この新規な構造のトランジスタはqの
ベース領域がqに対してベース抵抗20として寄与する
ため(CJ図の等価回路に示す如く比較的小さな補助ト
ランジスタQ、と比較的大きな主トランジスタqとが並
列接続されて榊成される。従ってこのトランジスタのh
yge性uQtトQt ソt1−ツレf) hyEe性
21 、22の総合された結果となシ、QlとQlの大
きさを過当に選定すると、 lcが小さい領域ではベー
ス電極17に近く位置しているQlが支配的に動作し、
lCの増加に伴ってqのhFEが低下してコレクターエ
ミッタ間電圧降下VCE(sat)Q、が増大するので
、l c rd Qtに支配的に流れる様になるo Q
lからqへの移行はベース抵抗20と% QlのhFE
特性の相互関係によって決定される。即ち、(C)図に
於てlcが小即ち1BがJ\の領域に於てはベース抵抗
rがIBIを抑制する為に、Q、に 1B:lB1+lB2            ・・・
・・・(1)1c=lcx−1−1cz       
        ・・・…(2)VBg(sat)Q、
=rxlBx+Vi+z(sat)Qg  −−−−−
・(s)lc:=hp、x1m           
   ・・・・・・(4)IcI =hFE1x IB
I             −e−(5)lC2=h
FE2 XIB!             ・・・・
・・(6)但し、VnE(sat)Qt :Qt のペ
ース−エミッタ飽和電圧、VnE(sat)C4: Q
a  のベース一二きツタ飽和電圧、IBI:Q、に流
れるペース電流、lB2:qに流れるベース電流、lc
l、Q、に流れるコレクタ電流、IC2:Q、に流れる
コレクタ電流、hpl、1: Qtの電流増巾率、hF
+、+ : Qtの電流増巾率、支配的に流れるので、
コレクタ電流もlC1が支配的となるが、lcが犬即ち
IBが犬の領域に於てはVaE(sat)Q、がIBI
  の増加に伴って増大する為、(8)式で決まるlB
2が蟻を駆動する様になって、lC2が支配的になる。
Next, a transistor according to an embodiment of the present invention is shown in FIG.
To explain with reference to d), after forming the collector layers 11 and 12 and the base layer 13 in the same manner as in the conventional method,
The emitter layer is divided into two regions, and the first emitter layer 18 and the second emitter layer 14 are formed by selective diffusion of donor impurities, and the auxiliary transistor section Q
, and the main transistor part Q! Then, by depositing a collector electrode 15, an emitter electrode 16, and a base electrode 17, the collector and emitter of the auxiliary transistor Q and the main transistor q are short-circuited by a common electrode, and at the same time, the auxiliary transistor Q1 is connected to the base electrode. The base layer 13 is placed between the main transistors q and the emitter electrode 16.
The device is manufactured by providing an insulating film 19 to prevent short circuits. In the transistor with this new structure, the base region of q contributes to q as a base resistance 20 (as shown in the equivalent circuit of the CJ diagram, a relatively small auxiliary transistor Q and a relatively large main transistor q are connected in parallel). Therefore, h of this transistor is
This is the combined result of hyEe properties21, 22.If the sizes of Ql and Ql are excessively selected, in the region where lc is small, it will be located close to the base electrode 17. Ql that exists operates dominantly,
As lC increases, the hFE of q decreases and the collector-emitter voltage drop VCE(sat)Q increases, so that the current flows dominantly to l c rd Qt.
The transition from l to q is based on a base resistance of 20 and hFE of % Ql.
Determined by the interrelationship of characteristics. That is, in the region (C) where lc is small, that is, 1B is J\, the base resistance r suppresses IBI, so Q, 1B:lB1+lB2...
...(1) 1c=lcx-1-1cz
...(2) VBg(sat)Q,
=rxlBx+Vi+z(sat)Qg ------
・(s)lc:=hp,x1m
・・・・・・(4) IcI = hFE1x IB
I-e-(5)lC2=h
FE2 XIB!・・・・・・
...(6) However, VnE(sat)Qt: pace-emitter saturation voltage of Qt, VnE(sat)C4: Q
Base 12 saturation voltage of a, IBI: pace current flowing in Q, lB2: base current flowing in q, lc
Collector current flowing in l, Q, IC2: Collector current flowing in Q, hpl, 1: Current amplification rate of Qt, hF
+, +: Current amplification rate of Qt, since it flows dominantly,
The collector current is also dominated by lC1, but in the region where lc is dog, that is, IB is dog, VaE(sat)Q, is IBI
Since it increases with the increase of , lB determined by equation (8)
2 starts to drive the ants, and 1C2 becomes dominant.

以上の結果、Qt 、Qtがlcのレベルに応じて自動
的に動作レベルを変化させるので総合のhFEは(d)
図の23の如く平坦な特性’を得ることができる0以上
、2分割型トランジスタの例について説明したが、エミ
ッタの分割を2個以上に分割した場合でも効果は同様で
あって、第3図(aJ〜(clは3個分割の例を示し、
Qt 、 Qtは補助トランジスタ、qは主トランジス
タであって、動作の原理は2分割の場合と同様で、lc
依存性の少い平坦なhFE特性を得ることができる。
As a result of the above, since Qt and Qt automatically change the operating level according to the level of lc, the total hFE is (d)
Although we have described an example of a 0 or more, 2-split type transistor that can obtain a flat characteristic as shown in 23 in the figure, the effect is the same even when the emitter is divided into 2 or more pieces, as shown in Fig. 3. (aJ~(cl shows an example of dividing into 3 parts,
Qt, Qt are auxiliary transistors, q is the main transistor, and the principle of operation is the same as in the case of two divisions.
Flat hFE characteristics with little dependence can be obtained.

第4図+a)、 (blはダーリントン結合型トランジ
スタの出力段に於て本発明を適用した施であって、等価
回路は(b)図の如くになル、大電力用途で1c依存性
の少いトランジスタが実現できることは前記の説明から
明瞭である。
Figure 4 +a), (bl is the output stage of a Darlington coupled transistor to which the present invention is applied, and the equivalent circuit is shown in Figure 4 (b). It is clear from the above description that fewer transistors can be realized.

又、本発明の説明に当ってへ型半導体基板を使用した例
を示したが、P型半導体基板を使用する場合にはアクセ
プタとドナー不純物を入れ替えることによって逆のタイ
プのトランジスタkmることかできることは明白であり
、効果も全く同等である。更にペース電極の配置が中央
に位置される構造のトランジスタの場合にも、補助トラ
ンジスタを主トランジスタとベース電極との間にF!I
Imfkすることによル、本発明に依る効果が期待でき
ることは言うまでもない。
Furthermore, in explaining the present invention, an example using a hemi-type semiconductor substrate has been shown, but if a p-type semiconductor substrate is used, it is possible to create a transistor of the opposite type by replacing the acceptor and donor impurities. are obvious and have exactly the same effect. Furthermore, even in the case of a transistor with a structure in which the pace electrode is located in the center, the auxiliary transistor is placed between the main transistor and the base electrode. I
It goes without saying that the effects of the present invention can be expected by using Imfk.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(dlU従来のトランジスタの例であっ
て、第1図(a)はエミッタ側から見たパターンの平面
図、第1図(b)は第1図(a)のA−A’での断面図
、第1図(clは等価回路、第1図(dJは電流増巾率
hFEとコレクタ電流ICとの関係を示すグラフである
。 第2図(al〜+d)は本発明の一実施例であって、第
2、図(a)はエミッタ側から見たパターンの平面図、
第2図(b)は第2図(a)のに3−B’での断面図、
第2図(C)は等価回路、#!2図(d)はbFEとl
cとの関係を示すグラスである。第3図(a)〜(C)
は本発明の他の実施例であって、第3図(a)は素子断
面図、第3図(bJは等価回路、第3図(C1はhFo
とIcとの関係を示すグラフである0第4図(a) 、
 (b)はダーリントン結合型トランジスタの出力段に
本発明1に適用したさらに他の実施例であって、第4図
(a)は素子断面図、第4図(b)はその等価回路であ
る。 なお図において、1・・・・・・へ型半導体基板、2・
・・・・・コレクタ層、3・・・・・・ベース層、4・
・・・・・エミツタ層、5・・・・・・コレクタ金属電
極、6・・・・・・エミッタ金属電極、7・・・・・・
ペース金属電極、11.12・・・・・・コレクタ層、
13・・・・・・ベース層、14・・・・・・第2のエ
ミツタ層、15・・・・・・コレクタ電極、16・・・
・・・エミッタ電極、17・・・・・・ベース電極、1
8・・・・・・第1のエミツタ層、19・・・・・・絶
縁層、20・・・・・・ペース抵抗、21・・・・・・
Q、のhFE%性、22・・・・・・Q!のhFE特性
、23・・・・・・QsのhFE%性、である。 (a/) し くb”) 第1図 (C>           (tL’)第1図 (oJ) 第3図 第3図
Fig. 1(al~(dlU) is an example of a conventional transistor, Fig. 1(a) is a plan view of the pattern seen from the emitter side, and Fig. 1(b) is A-(dlU) of Fig. 1(a). A cross-sectional view at A', Fig. 1 (cl is an equivalent circuit, Fig. 1 (dJ is a graph showing the relationship between current amplification factor hFE and collector current IC), Fig. 2 (al to +d) is a graph showing the relationship between current amplification factor hFE and collector current IC. In one embodiment of the invention, the second figure (a) is a plan view of the pattern seen from the emitter side;
Fig. 2(b) is a cross-sectional view taken along line 3-B' of Fig. 2(a),
Figure 2 (C) is an equivalent circuit, #! Figure 2(d) shows bFE and l
This is a glass showing the relationship with c. Figure 3 (a) to (C)
3(a) is a cross-sectional view of the device, FIG. 3(bJ is an equivalent circuit, and FIG. 3(C1 is hFo
Figure 4(a) is a graph showing the relationship between Ic and Ic.
4(b) shows yet another embodiment of the present invention 1 applied to the output stage of a Darlington coupled transistor, FIG. 4(a) is a cross-sectional view of the element, and FIG. 4(b) is its equivalent circuit. . In the figure, 1... a hemi-shaped semiconductor substrate, 2...
... Collector layer, 3 ... Base layer, 4.
...Emitter layer, 5...Collector metal electrode, 6...Emitter metal electrode, 7...
Pace metal electrode, 11.12... Collector layer,
13... Base layer, 14... Second emitter layer, 15... Collector electrode, 16...
... Emitter electrode, 17 ... Base electrode, 1
8...First emitter layer, 19...Insulating layer, 20...Pace resistor, 21...
hFE% of Q, 22...Q! The hFE characteristics of 23...Qs are the hFE% characteristics. (a/) Shikub") Figure 1 (C>(tL') Figure 1 (oJ) Figure 3 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板の一生面側に一導電型不純物が拡散
されてコレクタ層が形成され、他主面側に逆導電型不純
物が拡散されてベース層が形成され、該ベース層内に一
導電型不純物が拡散されてエミツタ層が形成された半導
体装置において、前記ベース層内にその平面形状が前記
エミッタmtとシ囲む如く形成され九−導電型不純物領
域が設けられていることを特徴とする半導体装置。
Impurities of one conductivity type are diffused on the main surface side of the semiconductor substrate of one conductivity type to form a collector layer, impurities of opposite conductivity type are diffused on the other main surface side to form a base layer, and one conductivity type is formed in the base layer. A semiconductor device in which an emitter layer is formed by diffusion of type impurities, characterized in that a nine-conductivity type impurity region is provided in the base layer so that its planar shape surrounds the emitter mt. Semiconductor equipment.
JP379782A 1982-01-13 1982-01-13 Semiconductor device Pending JPS58121671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP379782A JPS58121671A (en) 1982-01-13 1982-01-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP379782A JPS58121671A (en) 1982-01-13 1982-01-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58121671A true JPS58121671A (en) 1983-07-20

Family

ID=11567179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP379782A Pending JPS58121671A (en) 1982-01-13 1982-01-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58121671A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008531973A (en) * 2005-03-15 2008-08-14 スカニア シーブイ アクチボラグ(パブル) Cooling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008531973A (en) * 2005-03-15 2008-08-14 スカニア シーブイ アクチボラグ(パブル) Cooling system

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