JPS58121647A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten time required for the process of forming a wiring pattern, and to correct wiring connecting semiconductor elements formed easily when the wiring is damaged by previously forming a wiring film, into which a MOS transistor is interposed, on its midway of the wiring connecting the elements. CONSTITUTION:The floating gate type MOS transistors 12A, 12 are interposed on its midway of the wiring 11A, 11 of a wiring region 1 section connecting the semiconductor elements, and the wiring is connected to the source regions 18 and drain regions 14 of the transistors. Voltage is applied among the source regions 18 and drain regions 14 of the MOS transistos formed among the wiring 11A of sections to be connected in these MOS transistors such as transistors 12A of interest shown in fig. 3 in 12A by using a ROM writer, etc. Accordingly, charges 16 are formed into a Si substrate under the floating gates 15 of the transistors, thus resulting in the conductive state of the wiring 11A by the charges.

Description

DETAILED DESCRIPTION OF THE INVENTION (f) Technical Field of the Invention The present invention relates to an improvement of a master-swiss type semiconductor device.

BACKGROUND OF THE INVENTION In recent years, there has been a demand for semiconductor devices in which users can configure logic circuits as needed. Since the circuit configuration of these semiconductor devices varies depending on the user's order, a high-mix, low-volume production method is not required.
The master slicing method is now used, in which the semiconductor device is manufactured immediately after the diffusion process after receiving the order from the user.

(0) It consists of an element region 2 in which a MOS type F-Tun ν star, etc., which constitutes a problem with the prior art, is formed, and a wiring region 8 that connects these elements. By the way, when forming these semiconductor devices using the master slicing method, generally after forming source/drain regions in a predetermined pattern on an 81 substrate, forming 5xos@ for gates on the substrate, and then applying a V reconverter to the pole. The formed 81 substrate is prepared in advance.

After receiving the user's order, we immediately form a nine-metal/L/minium (Aj) wiring film by vapor deposition to connect these semiconductor elements, and then apply photoresist (after coating the film) on the vapor deposition film. A photoresist film is formed in a predetermined pattern by photolithography, and then a metal film is subjected to Pfusma etching using the patterned photoresist film as a mask to form a wiring pattern for connecting elements. However, with this method, the process to form the wiring pattern of the predetermined pattern described above is too time-consuming, and the semiconductor device once formed may be defective and the wiring between elements may be interrupted. Even if you try to correct it, it will result in defects that cannot be corrected.

■Object of the Invention The present invention eliminates the above-mentioned drawbacks, shortens the time required for the process of forming the wiring pattern, and provides a semiconductor that can be easily corrected in the event of a defect in the wiring connecting the formed elements. The purpose is to provide the structure of the device.

(61) Structure of the Invention In order to achieve the above object, the semiconductor device of the present invention has a floating goo (MOS) fungistor interposed in advance in the middle of a coupling wiring that connects semiconductor elements formed on a semiconductor substrate. connecting the source and drain regions of the transistor to the coupling wiring, and generating a charge in the substrate under the gate region of the circuit transistor installed at the location where the connection is to be made between the semiconductor elements; The present invention is characterized in that a predetermined wiring is made conductive to connect the semiconductor elements.

B. Embodiment of the Invention An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a plan view showing the main parts of the semiconductor device of the present invention, particularly showing the above-mentioned coupling wiring area, and FIG.
The figure is an enlarged cross-sectional view of a portion of FIG. 2.

As shown in FIG. 2, the semiconductor device of the present invention is different from the conventional device in that the above-mentioned semiconductor devices are connected to each other in the wiring region 10, where there is floating goo (glue floating in the middle of the wiring 11A, 11O) [
MOS) One ν Star 12! A, ll are interposed therebetween, and the source region 18 and drain region 14 of the transistor are connected to each other.

These MOS) MOs formed between the wiring 11A of the part to be connected in the fan ν star 12
S.) In a transistor such as IgA, as shown in FIG. 8, a voltage is applied between the source region 1B and drain region 14 of the transistor IgA using, for example, a ROM filter. Then this transistor's floating game 1
A charge 16 is formed in the substrate 81 below the substrate 15, and the wire 11A becomes conductive due to this charge.

This MOS type Tofunsister 12A is connected to the program map y.
v It is easily formed in the same process when forming a MOS semiconductor device.

By doing this, the wiring at the part where you want to make the desired connection will not be in a conductive state.If you form the wiring film with the MOS fungistar in advance like this, even if the user orders it. A desired circuit can be formed immediately, and even if a wiring pattern is formed incorrectly, it can be corrected.

(2) Effects of the Invention As described above, the semiconductor device of the present invention has the advantage that the semiconductor device can be easily formed in a short period of time after the user's approval.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the structure of a conventional MOS [semiconductor device].
FIG. 2 is a plan view of a main part of the semiconductor device of the present invention, and FIG. 8 is a sectional view of FIG. 2. In the figure, 1 is an 81 substrate, 2 is an element area, 8 is a wiring area, 11.11A is a wiring, 12, 12A FiMOS) fungistor, 18.14 is a source and drain area, 1
5 indicates a floating gate, and 16 indicates a charge.

Claims (1)

[Claims] A floating M○S transistor is interposed in advance in the middle of the coupling wiring connecting semiconductor elements formed on the semiconductor substrate, and the source/drain region of the transistor is connected to the TS common #13m. , a charge is generated in the substrate under the gate region of the transistor installed in a place where the connection is made between the semiconductor elements, and a predetermined wiring for coupling is made conductive to connect the semiconductor elements. A semiconductor device characterized in that: