JPS58121633A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58121633A JPS58121633A JP358282A JP358282A JPS58121633A JP S58121633 A JPS58121633 A JP S58121633A JP 358282 A JP358282 A JP 358282A JP 358282 A JP358282 A JP 358282A JP S58121633 A JPS58121633 A JP S58121633A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- solder material
- thin film
- base
- small
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体素子の裏面に金属薄膜層を形成し、
基台にろう材によシ接合された半導体装置に関する。[Detailed description of the invention] This invention forms a metal thin film layer on the back surface of a semiconductor element,
The present invention relates to a semiconductor device bonded to a base using a brazing material.
従来のこの種の半導体装置は、第１図に模式正面で示す
ようになっていた。（１）はシリコン基体からなる半導
体素子で、裏面には全面にメタライズにより金属薄膜層
（２）が形成されである。（３）は鋼合金材製のリード
フレームからなる基台で、グイパッド部上に鉛すず系の
はんだなどのろう材（４）Ｋよシ半導体素子（１）を接
合固着している。A conventional semiconductor device of this type is shown schematically from the front in FIG. (1) is a semiconductor element made of a silicon substrate, and a metal thin film layer (2) is formed on the entire back surface by metallization. (3) is a base made of a lead frame made of a steel alloy material, and a brazing material (4) such as a lead-tin solder is bonded and fixed to the semiconductor element (1) on the lead frame.
シリコン基材へのろう材（４）の接合力がほとんどない
ため、半導体素子（１）の裏面に金属薄膜層（２）を形
成しである。Since the brazing material (4) has almost no bonding force to the silicon base material, a metal thin film layer (2) is formed on the back surface of the semiconductor element (1).
半導体素子（１）の基台（３）への装着は、次のようｋ
すゐｏｆず、基台（３）をろう材（４）の融点（２００
−３００℃）以上に加熱し、ろう材（４）を上面に置き
溶融させ、この上に半導体素子（１）を載せ押付ける。The semiconductor element (1) is mounted on the base (3) as follows.
The base (3) is heated to the melting point of the brazing filler metal (4) (200
-300[deg.] C.) or higher, a brazing filler metal (4) is placed on the top surface and melted, and a semiconductor element (1) is placed on top of this and pressed.
溶融したろう材（４）が金属薄膜層（２）と基台（３）
とに十分くぬれた後、常温に戻す◎ろう材（４）は融点
（２ｏＯ〜３００℃）以下になると固相になシ、半導体
素子（１）は基台（３）に固着される。The molten brazing filler metal (4) is applied to the metal thin film layer (2) and the base (3).
After being thoroughly wetted, the temperature is returned to room temperature. When the brazing material (4) becomes below its melting point (2oO to 300°C), it becomes solid, and the semiconductor element (1) is fixed to the base (3).
シリコンの線膨張係数は４〜５ＸＩＯ＝／’Ｃであり、
鋼合金の線膨張係数は１６〜１８Ｘｌｏ−’／’Ｃであ
るので、ろう材（４）の固相が始まる温度から常温にな
るまでの温度差により、半導体素子（１）には熟ひずみ
が発生する。しかし、−辺長が５〜６ ｍｍ以下の半導
体素子（１）であれば、ろう材（４）自体が変形するこ
とＫより熱ひずみが吸収され、半導体素子は支障が生じ
ない。The linear expansion coefficient of silicon is 4~5XIO=/'C,
Since the linear expansion coefficient of the steel alloy is 16 to 18Xlo-'/'C, the semiconductor element (1) undergoes ripening strain due to the temperature difference between the temperature at which the solid phase of the brazing filler metal (4) begins and the temperature reaches room temperature. Occur. However, if the semiconductor element (1) has a side length of 5 to 6 mm or less, the thermal strain is absorbed by the brazing material (4) itself being deformed, and the semiconductor element does not suffer any trouble.
しかし、半導体素子（１）の−辺長が５〜６ ｍｍを超
えたものであれば、上記従来の装置では、ろう材（４）
は熱ひずみを吸収しきれず、半導体素子（１）に熱応力
が発生し、変形や破損が生じていた０この発明は、上記
従来装置の欠点を除去するためになされたもので、半導
体素子の裏面に小面積宛の金属薄膜層を複数個所に分散
して形成し、基台へのろう材接合による半導体素子の熱
ひずみを防止し、変形や破損をなくすることを目的とし
ている。However, if the side length of the semiconductor element (1) exceeds 5 to 6 mm, the conventional apparatus described above cannot
cannot absorb thermal strain, and thermal stress occurs in the semiconductor element (1), resulting in deformation and breakage. This invention was made to eliminate the drawbacks of the above-mentioned conventional device. The purpose of this is to form a small-area metal thin film layer distributed over multiple locations on the back surface to prevent thermal distortion of the semiconductor element due to solder metal bonding to the base, and to eliminate deformation and damage.
８２図はこの発明の一実施例による半導体装置の模式正
面図である０シリコン基体からなる半導体素子（１）は
−辺長が５〜６ ｍｍを超えており、裏面には、直径約
０．３ｘ＋ｕｎの小径の点状のメタライズによる金属薄
膜層（ロ）が多数箇所に分散配置して形成されである。FIG. 82 is a schematic front view of a semiconductor device according to an embodiment of the present invention. A semiconductor element (1) made of a silicon substrate has a side length of more than 5 to 6 mm, and a back side with a diameter of about 0.0 mm. The metal thin film layer (b) is formed by dot-shaped metallization with a small diameter of 3x+un and is dispersed at many locations.
上記従来の場合と同様に、基台（３）を加熱（２００〜
３００℃）以上に加熱し、ろう材（６）を上面のダイノ
くラド部に置き溶融させ、この上に半導体素子（１）を
載せ押付ける。溶融したろう材（２）は半導体素子（１
）の各金属薄膜層（ロ）に接合し、シリコン面には接合
しなく多数の空所（至）ができる。常温に戻ると第２図
のように１半導体素子（１）の熱ひずみが、ろう材（６
）の外周側の破断ろう材部α◆を生じさせることＫよシ
逃がされる。As in the above conventional case, heat the base (3) (200~
The brazing material (6) is placed on the top surface of the die and melted, and the semiconductor element (1) is placed and pressed onto it. The melted brazing filler metal (2) is applied to the semiconductor element (1).
) is bonded to each metal thin film layer (b), and many voids (to) are created without bonding to the silicon surface. When the temperature returns to room temperature, as shown in Figure 2, the thermal strain of one semiconductor element (1) causes the brazing material (6
) is released to avoid causing a fractured brazing filler metal part α◆ on the outer circumferential side.
シリコン基材からなる半導体素子（１）を、鋼合金から
なる基台（３）にろう材（６）Ｋよシ溶着すると、熱ひ
ずみにより半導体素子（１）を変形させる応力が発生す
る。この応力は中心部ではほぼＯ−であるが周辺に近づ
くにしたがって大きくなる。金属薄膜層（ロ）の直径が
０．３ｍｍと小さいため、ろう材（２）の破断強度は小
さい。したがって、周辺部のろう材（至）が破断し破断
ろう材部Ｑ４が生じることにより、半導体素子（１）の
熱ひずみが逃され、変形や破損がなくなる。When a semiconductor element (1) made of a silicon base material is welded to a base (3) made of a steel alloy with a brazing material (6) K, stress is generated that deforms the semiconductor element (1) due to thermal strain. This stress is approximately O- in the center, but increases as it approaches the periphery. Since the diameter of the metal thin film layer (b) is as small as 0.3 mm, the breaking strength of the brazing filler metal (2) is small. Therefore, the brazing filler metal (to) in the peripheral portion is broken and a broken brazing filler metal portion Q4 is generated, whereby the thermal strain of the semiconductor element (1) is released, and deformation and damage are eliminated.
なお、上記実施例では、金属薄膜層（イ）は直径約０．
３ｍｍの点状にして多数箇所に設けたが、半導体素子（
１）の熱ひずみを逃がし変形を与えなりような、他の大
きさと筒数にすることができる。実測によれば、大きさ
は直径約１ｍｍ以内が適当である。In the above embodiment, the metal thin film layer (a) has a diameter of approximately 0.0 mm.
Although 3mm dots were placed in many locations, the semiconductor element (
It is possible to use other sizes and numbers of cylinders so as to release the thermal strain in 1) and provide deformation. According to actual measurements, the appropriate size is within about 1 mm in diameter.
また、半導体素子はシリコン基体の外の基体であっても
よく、基台はリードフレームのグイパッドの外、ガラス
エポキシ基板やセラミック基板など種々の基台で金属層
が設けられた場合にも適用できる。In addition, the semiconductor element may be a substrate other than a silicon substrate, and the base can be applied to various types of bases such as glass epoxy substrates, ceramic substrates, etc., other than the lead frame's lead frame, and a metal layer is provided. .
さらに、ろう材としては、はんだに限らず金シリコンろ
う材などのろう材などを用いた場合にも適用できる。Furthermore, the brazing material is not limited to solder, and may be applied to brazing materials such as gold-silicon brazing material.
以上のように、この発明によれば、半導体素子の裏面に
、小面積宛の金属薄膜層を複数箇所に分散して形成した
ので、基台へのろう材接合による半導体素子の熱ひずみ
が逃され、変形や破損が防止される。As described above, according to the present invention, a thin metal film layer with a small area is formed in multiple locations on the back surface of a semiconductor element, so that the thermal strain of the semiconductor element caused by bonding the brazing material to the base can be avoided. to prevent deformation and damage.
第１図は従来の半導体装置を示す模式正面図、第２図は
この発明の一実施例による半導体装置を示す模式正面図
である０
１・・・半導体素子、３・・・基台、１１・・・金属薄
膜層、１２・・・ろう材
なお、図中同一符号は同−又は相当部分を示す。
代理人 葛野信−（外１名）FIG. 1 is a schematic front view showing a conventional semiconductor device, and FIG. 2 is a schematic front view showing a semiconductor device according to an embodiment of the present invention.01...Semiconductor element,3...Base,11 . . . Metal thin film layer, 12 . . . Brazing material. In the drawings, the same reference numerals indicate the same or corresponding parts. Agent Shin Kuzuno (1 other person)
Claims (2)
個所に分散して形成し、基台上にろう材を介して接合し
て固着してあり、上記ろう材の溶着による上記半導体素
子の熱ひすみ変形を防止したことを特徴とする半導体装
置〇(1) A thin metal film layer with a small area is formed in multiple locations on the back surface of a semiconductor element, and is bonded and fixed onto a base via a brazing material, and the semiconductor element is formed by welding the brazing material. A semiconductor device characterized by preventing thermal strain deformation of the element〇
内の点状に形成しであることを特徴とする特許請求の範
囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein each of the metal thin film layers is formed in the form of a dot having a diameter of about #1 mm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP358282A JPS58121633A (en) | 1982-01-12 | 1982-01-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP358282A JPS58121633A (en) | 1982-01-12 | 1982-01-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58121633A true JPS58121633A (en) | 1983-07-20 |
Family
ID=11561442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP358282A Pending JPS58121633A (en) | 1982-01-12 | 1982-01-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58121633A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2656193A1 (en) * | 1986-12-19 | 1991-06-21 | Telecommunications Sa | Method of mounting a semiconductor chip on a thermal dissipation and electrical connection support |
| US5093281A (en) * | 1988-07-13 | 1992-03-03 | Mitsubishi Denki Kabushiki Kaisha | method for manufacturing semiconductor devices |
-
1982
- 1982-01-12 JP JP358282A patent/JPS58121633A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2656193A1 (en) * | 1986-12-19 | 1991-06-21 | Telecommunications Sa | Method of mounting a semiconductor chip on a thermal dissipation and electrical connection support |
| US5093281A (en) * | 1988-07-13 | 1992-03-03 | Mitsubishi Denki Kabushiki Kaisha | method for manufacturing semiconductor devices |
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