JPS58121449A - Square root operating circuit - Google Patents

Abstract

PURPOSE:To reduce the required number of ROMs and simplify the circuit configuration and the selective control of the ROMs, by admitting a part of the error of X corresponding to an error which is admitted to the Y to the X when Y=X1/2 is found. CONSTITUTION:A decoder 5 inputs four higher-order bits (2<14>-2<11> bits) of an input X, and outputs a chip select signal CS1 when the logic of all bits is ''0'', and outputs another chip select signal CS2 when the logic of all bits is not ''0''. An ROM (6-2) inputs eleven higher-order bits out of fifteen bits of binary numbers which represent the input X as an address, and the LSB of the address is regarded as numbers of 2<m> (m=15-11) and stores as binary number data representing square roots of the numbers at location assigned by the address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a square root calculation circuit in digital calculation.

ROM (ROM) is often used as a square root calculation circuit.
There is a function conversion device configured with a read-only memory (read-only memory) or the like. 2 representing X
RO that inputs all base numbers and outputs Y=JT'ce binary numbers
As M, the data at address X is Y=v/Yt-
Just store it. Figure 1 shows an example of the contents of a ROM used for square root calculations. In the figure, (1) is an address and 12) is data. Input X is expressed as an 11-bit binary number, the LSB (least significant bit) of which is l, and when address (1) is fully specified, data (2) on the right side thereof is read out. In this case, the data is 8 bits (the upper 2 bits are not required).

However, it is included for reasons explained later), and LSB=1. The relationship Y=JY is calculated in advance, and the calculated values of Y less than l are rounded down by 4 to 5, and the results are written in the ROM.

By the way, if the input data Divided into 16 areas and 11 areas for each area.
The ROMt-allocation of bit inputs and which ROI VI money to use are determined by the chip select signal.

In general, in a ROM with n-bit input, we get the square root Y=JX for X with =m+n-bit input, and the name is 2rr' R
The chip select signal may be generated using the upper m bits of the bits.

Figure 3 shows all the contents of the ROM shown in Figure 2, step 2: υ,
(21 corresponds to the same reference numerals in FIG. 1, and 4G indicates the upper 4 bits that generate the chip select signal.

Figure 24 is a block diagram showing a conventional circuit board (3 is a decoder, 141 is a function conversion device, and (4-1) to (4-16)
It is composed of 16 ROMs shown in ). Each ROM is '
The processing range for 11-bit input is as shown in FIG. The input
Even in ROM (4-1), etc., which do not require bits, the output is aligned to 8 bits.

The upper 4 bits of the input are input to the decoder (3) and C
It is output as 16 types of chip select signals from 8I to C816, and is input in parallel to 16 ROMs of lower 11 bits, but only 7tROM is operated by inputting the chip select signal, and the output of each ROM is determined by wired OR to the value of the square root Y. is extracted as For example, input X is r (1
001,0OOOOIOIIIJ, the upper 4 bits r 0001 J select ROM (4-2) and the lower 11 bits r 00000010111
J is entered as address and Y = r 0010111
0 J is output.

This corresponds to i-46 when expressed in lO base.

Since the conventional circuit is configured as described above, the difference between the number of bits of the input value and the number of bits of the ROM n is m = k
If -n, how many ROMs are required? □There is a drawback that the number of required ROMs increases exponentially as m becomes larger.

As is clear from Figure 3, the address r 0000
0000000 J to r 00000010110
The data between n addresses up to J has the same content and is RO
There was a drawback that M was inefficiently used. If an error of g is allowed for Y, exactly Y=JX and Y◆E=947−
Second? ! :T, then ΔX=2YE◆E” middle 2YE
For example, if E=±0.5 and Y=45, the range of X that gives the same Y is X±45 (1981~
2070), but ROM (4-1) to (4-16)
This is because all inputs are LSB=1.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by allowing a part of the error corresponding to the error allowed in the output value for all input values, the RO
It is an object of the present invention to provide a square root calculation circuit that can significantly reduce the required number of M, has a small circuit scale, and has a simple configuration and control.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of the present invention, where the numerical range and bit configuration of input X and output Y are the same as in FIG. 4, (51 is a decoder, (6) is a function conversion device, The decoder (5) decodes the upper 4 bits (214
~211 bits) and the logic of all bits is all “O”.
'', the chip select signal C8I is output; otherwise, the chip select signal C82t- is output. (
6-1) f-1 OL OROM (generally an OL function conversion device), (6-2) is a second ROM (generally a second function conversion device). ROM (6-1) is RO
It is the same as M(4-1), and its contents are as shown in FIG. 1, for example. ROg (6-2) is the upper 11 bits of the 15 bits of the binary number 214 to 2 representing input X, that is, 2
~ It is a ROM that inputs as a 2-bit t-address and stores as data a binary number representing the square root of the address, considering it as a binary number with the LSB of 2 at the location specified by that address.For example, in Figure 16. It is configured as follows.

In Figure 16, (lυ is an address, and (21) is data.

The top row of the address 11υ is the same as 4G in FIG. 3 by (1) fully concatenating and removing the lower 4 bits of (1). In the example in Figure 16, even if the address from which the lower 4 bits of X are removed is used, the top three rows will still be data.
As will be seen, the circuit shown in FIG. 5 can also calculate the square root with the same precision as the circuit shown in FIG.

Note that in the above example, k = 15, m = 4,
n = 11.

Although numerical examples of E=±0.5 have been described, it is clear that the present invention is not limited to these numerical examples.

As described above, according to the present invention, the square root of X y = l
'X corresponding to the YK allowable error when finding E
By allowing a fraction of the error t−X in the ROM
This has the effect that the required number of circuits can be significantly reduced, the circuit configuration and ROM selection control can be simplified, and the cost can be reduced.

[Brief explanation of drawings]

Figure 1 shows an example of the contents of a ROM used for square root calculations, Figure 2 shows the input range shared by multiple ROMs, and Figure 3 shows the contents of one of the ROMs shown in Figure 2. Figure 4 is a block diagram showing an example of a conventional circuit, Figure 5 is a block diagram showing an embodiment of the present invention, and Figure 6 is a diagram showing the contents of one of the ROMs shown in Figure 5. It is. (5)...decoding circuit, (6-1)...first function conversion circuit, (6-2)...second function conversion circuit. Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3 Figure 4 C5I-C516 Figure 5

Claims (1)

[Claims] If m and n are arbitrary positive integers, in a square root arithmetic circuit that calculates the square root of a binary number of @k = man bits, is the logic of the upper m bits of the input binary number all rOJ? If the decoder circuit determines whether or not the upper m bits are all "0", the lower n bits of the above input binary code are manually calculated as t - the lower n bits of the input lower n bits. a function conversion device that outputs a binary number that represents the square root corresponding to the binary number with a predetermined precision;
In the above decoder circuit, when it is determined that even if the upper m bits are input, 1 bit is rxJ, the upper n bits of the input binary number are input, and the binary 151 least significant bit of the input upper n bits is 2m. A square root arithmetic circuit comprising: a second function converting device that outputs a binary number that is regarded as a certain binary number and is represented by a square sheet metal with the predetermined precision that corresponds to this number.