JPS58119058A - Error processor for dual memory device - Google Patents

Abstract

PURPOSE:To perform error recovery processing immediately if an error occurs to a dual memory device during access to the memory device, by reporting the error to a maintenance processor while informing a processing processor that access is normal. CONSTITUTION:If an error occurs to one memory device 5d, an error report signal 26d is sent out and during reading operation, normal read data 27c of a memory device 5c is selected while read data 17a is sent back to the processing processor 2. Further, an error report signal 16a is not sent out to the processing processor 2 and an error report signal 16b is sent out to the main processor 3. After end signals 25c and 25d are both obtained, an end signal 15a is returned to the processing processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error processing device for a dual memory device.

Error handling for duplicated memory devices means that if one memory device fails, it can be covered by the other memory device, and if an error is reported to the processor that accessed it, the original processing will be resumed. Because of the interference, a normal report is sent to the processing processor. However, if the error is left as it is, the reliability will decrease, so conventionally, when an error occurs, the information is frozen, and a maintenance processor or the like periodically patrols and checks the information to prevent the error from occurring. When there was a problem, a method was used to handle the error. However, in this method, there is a large time gap between error occurrence and error processing, so there is a high probability that the system will go down. Furthermore, if the interval between patrol checks is shortened, this probability can be lowered, but this increases the amount of check processing, which interferes with the original processing and reduces the processing capacity of the entire system, which is undesirable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that quickly processes an error that occurs in one of the duplex memory devices.

A feature of the present invention is that when an error occurs in one memory device while a processing processor is accessing a duplex memory device, a normal report is sent to the processing processor, and the error is also reported to the maintenance processor. , the maintenance processor handles errors.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing the overall configuration, in which a processing processor 2 and a maintenance processor 3 in a computer 1 are connected to duplex memory devices 5C and 5d through a memory control circuit 4.
access. FIG. 2 is a detailed internal configuration diagram of the memory control circuit 4. As shown in FIG. In the figure, 11 is a memory activation signal from the processor, 12 is a read/write signal from the processor, 13 is an address from the processor, 14 is write data from the processor, 15 is an end signal to the processor, and 16 is the processor 17 is read data to the processor, and 18 is an error freeze information read request from the maintenance processor 3.

Note that the signal lines a and b of the signal lines 11 to 17 are respectively connected to the processing processor 2. An interface with the maintenance processor 3 is shown. Further, 21 is a memory activation signal to the memory device, 22 is a read/write signal to the memory device, 2
Address to the 3Fi memory device, 24 is write data to the memory device, 25 is an end signal from the memory device, 26
is an error report signal from the memory device, and 27 is read data from the memory device.

Note that c and d of the signal lines 21 to 27 indicate interfaces with the memory devices 5c and 5d, respectively.

Next, the operation when an error occurs in one of the memory devices during access from one processor 2 will be explained. When the memory activation signal 11a is issued from the processing processor 2,
Memory activation signal 11b from maintenance processor 3
If the error freeze information read request 18 is not issued, the memory device 5 is read through the gates 31 and 33 in FIG.
Memory activation signals 21c and 21d are output to signals 21c and 55d.

At the same time, read/write signals 22 c, 22 d and address 2 are transmitted through selectors 34, 35, and 36.
3c, 23d, write data (only when writing) 24c,
24d is issued. Then, read data (only when reading) 27 C, 27 d from the memory devices 5 C, 5 d,
End signal 25c along with error report signals 26c and 26d
, 25d are returned. Here, if one memory device 5d causes an error and the error is 9, the 2-report signal 26d is output, so the selector 37 selects the normal read data 27c of the memory device 5C at the time of reading, and processes it through the selector 38. Processor 2 read data 17
a is returned. Further, the error report signal 16m is not outputted to the processing processor 2 by the gate 39, and the gate 4
0, an error report signal 16b is issued to the maintenance processor 3. Then, when the end signals 25c and 25d reach the 9th stage, the end signal 15a is returned to the processor 2 through game 41 and 42. Furthermore, since the error report signal 16b has been issued, the current address is set in the register 45 by the gate 43, and the end signal 15b is also issued to the maintenance processor 3 through the gate 44.

The maintenance processor 3 monitors the end signal 15b and the error report signal 16b, and when an error occurs, it immediately outputs the error freeze information read signal 18, reads out the addresses in the register 45, and starts error processing. do. If the error is recoverable, the maintenance processor 3 performs recovery processing, and if it is not possible, the maintenance processor 3 performs processing to disconnect the memory device that caused the error. During this time, the processing processor 2 can continue processing.

According to the present invention, even if one of the redundant memory devices fails, the processing processor can continue the process being executed, and error recovery processing is immediately performed, resulting in a highly reliable system. I can do it.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, and FIG.
It is a detailed configuration diagram thereof.

Claims (1)

[Claims] 1. In error handling of two duplicated optical memory devices accessed by a computer processor including a processing processor and a maintenance processor, while the processing processor is accessing the memory device, one of the memory devices Even if an error occurs, it is reported normally to the processing processor,
An error processing device for snow making with dual memory, characterized in that the error processing device is configured to report the error to the maintenance processor.