JPS58119056A - Data processor - Google Patents

Abstract

PURPOSE:To recover an error, by varying the voltage value of a data processing circuit immediately and allowing error recovery processing and executing retrial, at the error restoring time. CONSTITUTION:When a rereadout instruction containing a data record number where an error occurs is sent out from a host device 1, a write and readout instruction decoding circuit 3A stores the rereadout instruction in a reread instruction storage circuit and a device control circuit 4 is placed in readout mode through a signal line (c). Consequently, when data is read out of a device 5, characteristics of logical elements that a device control circuit 4 and an interface control circuit 2 use are varied and the device control circuit 4 makes an error check on whether the rereadout instruction is executed normally or not. When no error is detected by the error check, an error recovery is judged from variation in voltage value to proceed to succeeding data processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing apparatus, and particularly to a data processing apparatus characterized by microprogram control in error recovery.

Conventionally, in this type of data processing device a, when a data error occurs during data processing, if the error is caused by floating matter such as dirt or dust, the error may be recovered by retrying the error recovery. However, if the cause is due to deterioration of the logic element or the like, there is a drawback that the error cannot be recovered by simply repeating the error recovery retry command.

Therefore, an object of the present invention is to provide a data processing device that is capable of recovering from an error by retrying error recovery even when the cause is a defect in a logic element, depending on the degree of the defect. be.

In order to achieve the above object, the data processing apparatus of the present invention is capable of performing error recovery processing by completely changing the voltage value of the data processing circuit immediately after waiting for error recovery processing.

According to the present invention, an interface control circuit that transmits and receives signals to and from a higher-level device, a device control circuit that transmits and receives signals between this interface control circuit and between lower-level devices, and the interface control circuit. a write/read command decoding circuit that decodes a command from the higher-level device received from the upper-level device and sets the device control circuit to a write or read mode; In a data control device that performs write/read operations and also issues a reread command when an error is detected to cause all errors to be retried, there is a command in the command of the host device listed in item 11 that indicates that when an error is retried, A voltage value change command is included to change the voltages of the interface control circuit and device control circuit to set the error retry mode, and the write/read command decoding circuit is configured to change the voltage value of the reread command. A re-read command storage means for storing the re-read command, and a comparison means for comparing the stored re-read command with the next re-read command, further decode and store the voltage value change command, and the output thereof is and a voltage value change command decoding circuit which is also controlled by the output of the comparison means.

There is obtained a data processing device characterized in that it further comprises voltage control means for changing the voltage value of the power supply circuit in accordance with the output of the voltage value change command decoding circuit.

Next, the present invention will be explained in detail using examples.

FIG. 1 is a simple block diagram of an external storage control device that is an embodiment of the present invention. In FIG.

The host device 1 sends commands through the data/command signal line a. The sent command is received by the interface control circuit 2 and sent to the write/read command decode circuit 3A through the data/command signal line. This write/read command decoding circuit 3A analyzes all the processing contents, and if it determines that the contents of the command are data writing, it sets the device control circuit 4 to all write mode through the command line C, and receives data from the host device 1. All data are sent to the device 5, which is a lower-order device, through the data line, and if it is determined that the content of the command is to read data, the device control circuit 4 is set to read mode through the command line C. Device control circuit 4 is device 5
The receiver sends the data sent from the interface control circuit 2 through the data/command signal line b' to the interface control circuit 2, and also performs an error check. If an error occurs, an error report signal is sent to the interface control circuit 2 via the error detection line ek.

When the interface control circuit 2 receives data, it transfers all data to the host device 1 through the data/command signal line a, and when it receives an error report signal, it sends it to the host device 1 through the error report MfTh.

When the host device 1 receives the error report signal, it sends a voltage value change command to the interface control circuit 2 through the data/command signal line a as an error recovery means. The interface control circuit 2 sends the received voltage value change command to the voltage value change command decode circuit 3B through the signal line. The voltage value change command decoding circuit 3B determines the polarity of the voltage value change command, whether it is an increase or a decrease, and sends an instruction to the increase direction instruction circuit 6 if it is on the increase side, and to the decrease direction instruction circuit 7 if it is on the decrease side through the voltage value change instruction line g. do.

The increasing direction and decreasing direction instruction circuits 6 and 7 both have a circuit for storing the next command to be issued and a circuit that can change the voltage value when an error occurs again, and each of them has an increasing direction voltage value instruction. It instructs the power supply circuit 8 to change the predetermined voltage value through the line and the decreasing direction voltage value instruction line i. Upon receiving the instruction, the power supply circuit 8 changes the polarity (increase side, decrease side) and voltage value by the specified amount.

It is outputted to voltage IIj and supplied to the interface control circuit 2 and device control circuit 4 in preparation for the next reread command.

In the above description, it is assumed that the voltage change is a fixed value and is stored in each direction indicating circuit.

Further, the power supply circuit 8 is a power supply for the data processing circuit including the interface control circuit 2 and the device control circuit 4.

When a reread command containing an error data record number is issued from the host device under the above-mentioned condition, the write/read command decode circuit 3A reads the reread command and outputs the reread command to the reread command storage circuit (not shown in the figure). The device control circuit 4 is set to read mode from the signal line cK. With this, when reading data from device 5,
Device control circuit 4 and interface control circuit 2
Changes in the characteristics of the logic elements used in the system (for example, the switching speed becomes faster or slower, or element failures that used to be intermittent become fixed).

The device control circuit 4 checks whether the rereading command ends normally.
Perform error checking.

The above error check allows data processing without error detection. However, if an error is detected again, the error detection 11J e K instructs the increase/decrease direction instruction circuits 6 and 7 to change the voltage value again. At the same time, the host device IIJ'c also reports the occurrence of an error through the error report line f, and has the ninth reread command (re-read command) issued. Then, the write/read command decoding circuit 3A compares this re-read command and the stored previous command (re-read command) to see if the data record numbers match, and if the commands are the same, the voltage The value change decoding circuit 5B is instructed to change the voltage value by passing the instruction line gk to the increase/decrease direction instruction circuit 6.7 by logical product with the error detection line condition (error detection line e). This increase.

The decreasing direction instruction is transmitted through the signal line i and instructs the power supply circuit 8 to change the voltage value again. It should be noted that the above-mentioned circuit for comparing the re-reading commands and the logical product are used to perform the comparison, or the voltage change value reaches the limit value. By changing the power supply voltage value, error recovery means or normality confirmation can be easily realized. However, if the degree of error is so large that it is still detected even when the voltage change value reaches its limit, the two objects of the present invention cannot be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols: 1 is the host device, 2 is the interface control circuit, and 3A is the write/read command decoding circuit. 3B is a voltage value change command decoding circuit, 4 is a device control circuit, 5 is a device that is a lower-order device, 6 is an increase direction instruction circuit, 7 is a decrease direction instruction circuit, 8 is a power supply circuit e a -
J has all the various signal lines in a hailstorm.

Claims (1)

[Claims] 1. An interface control circuit that sends and receives signals to and from a higher-level device, a device control circuit that sends and receives signals to and from this interface control circuit and to lower-order devices, and a device control circuit that sends and receives signals from the interface control circuit. It has a write/read command decoding circuit that decodes commands from a higher-level device and sets the device control circuit in write or read mode 6, and controls the lower-level device according to the commands from the higher-level device to write and read data. In the data control device, when an error is detected, a reread command is activated to cause the error to be retried. A reread command memory includes a voltage value change command that changes the power supply voltage of the device control circuit and sets the mode to perform all error retries, and stores the reread command in the write/read command decoding circuit. and a comparing means for comparing the stored re-reading command and the next re-reading command, and further decoding and storing the voltage value changing command, the output of which is also controlled by the output of the comparing means. A data processing device comprising: a voltage value change command decoding circuit; and voltage control means for changing the voltage value of the power supply circuit in accordance with an output of the voltage value change command decoding circuit.