JPS58115684A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the data input and output ability of a dynamic type random access memory (D-RAM) by utilizing a data bus system connected to an external circuit effectively. CONSTITUTION:In a figure, Din and Dout are input and output data, and A0- A7 are address signals; and CAS' (casper) is a column address strobe, and WE' (write enable bar) is a write permit signal. Then, they are signals transferred between the D-RAM element and external circuit. An integrated circuit package 10 contains two memory blocks 12 and 14. The element 10 is fitted with wirings or terminal pins for signals RAS', CAs', WE', Din, and Dout, and addresses A0- A7, and the memory blocks 12 and 14 receive those signals, but one block 14 receives the signals RAS' and CAS' by inverting them through inverters 16 and 18. Consequently, active periods A and reset periods R are inverted between the memories 12 and 14 to realize successive data input and output operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, particularly a dynamic random access memory (D-RAM).

(2) Technical Background In D-RAM, there is an active period during which 1 is actually loaded or read, and a reset period for preparation. It is possible to write 9 or write. and generally t
1ml and 1x have the same length, so the period during which the memory is reading or writing is half of the total.

(3) Prior art and problems This does not mean that all resources such as data buses are utilized effectively.

(4) Objects of the Invention The present invention attempts to always use the data bus effectively by devising the structure of the memory.

(5) Configuration of the invention, that is, the semiconductor memory device of the present invention is configured as an integrated circuit, and (9) accommodates two memory blocks within the semiconductor memory device,
The address, input data, output data, write and write enable signals given externally to the memory device are directly given to both memory blocks in common, and both the row address strobe RAS and column address strobe CAS signals are sent to one memory block. directly to one memory block of the other, so that it gives through one memory block,
The present invention is characterized in that when one memory block is in an active period, the other memory block is in a reset period ttC, which will be explained next with reference to the drawings.

(6) Embodiment of the invention ig1 Figure is a diagram showing an outline of external connections and signal exchange of D-4AM configured as an integrated circuit, 10 indicates a package of the integrated circuit, and Vcc and Vis are power supply 1Dln.
%Dout u person, output data, Ao ~ person 1 is the address signal, CAS (cas bar) is the column address strobe, WE (write enable bar) is the write mode each signal, and these are the normal D-RAM elements and external circuits. All of the signals and power sent and received between Particularly in the memory cell section of the package, the central sense 7 is located as shown in Figure 6.
It consists of 718 people, a pair of pit lines extending left and right, a memory cell MC1, a word line WL, etc.
Of course, there are a large number of pit lines and words III, and a memory cell is arranged at each intersection thereof), and an address buffer, an address decoder, an I10 gate, etc. (not shown) are arranged as peripheral circuits. The sense amplifier is a driver transistor Q4. Q, a transistor that controls active and standby of the sense amplifier, a pit line sheet, and a transistor for precharging Qs,
Q4. Qγ is provided.

The operation of this memory element will be explained with reference to FIG.
When RAS falls, the memory enters an active period, and first a row address is taken in. That is, the row address buffer (not shown) takes in the row address h~m1 and outputs the address signal pits A, ~, T, and their inverted pi, Tom~.
In response to this, the row decoder connects word lines (word line WL on the real cell side and word line D on the dummy cell side).
WL) and select the memory cell t- connected to the word line.
It is connected to each pit line BL to cause the pit line potential to change in accordance with the stored content of the memory cell. Then CA
When S falls, the column address (also indicated by h to kC, that is, the address bus is used in a time-division manner) is taken in, and the column address buffer uAs ~ M D and M ~ A7
is sent to the column decoder, and the column decoder sends the pair of pins y)#(
! J Al, both dummy cells MO% DMC pit line BL,
BL) is connected to the data bus (not shown) specified by the column address, and according to the potential difference, the memory 1# information is sent to the output data Do through the input/output gate, etc.
When the extraction of ut (indicated by RD) begins, RAS rises, and the active period A ends and the reset period H begins. During the reset period, the clock Be becomes H and the transistors Qs -Qa, Q? is turned on, the pair of pit lines extending to the left and right of the sense amplifier S are short-circuited to the fourth position, and the lead source Ve6 is connected to perform grid charging. During the reset period, 4CCh S rises,
This completes the extraction of the output data Dout RDtff. The reset period R ends when RAS rises, and the memory enters an active period.

The above is about the continuous output mode, but the same is true for the honor write mode, except that input data Din is written into the selected cell at the time of [data read arrears] RD. 0°50.100 in the bottom row of Figure 2...
... indicates an example of the required time, and the unit is gu. The blank space sE of the timer DD4i is a period during which the address bus information may change in any way since address fetching has been completed. During the reset period R, since not only the memory cells but also the peripheral circuits of the D-RAM are dynamic, charging and discharging of the peripheral circuits in preparation for the next operation are also performed. As described above and as illustrated in FIG. 2, active a/! I length T mouth] and reset period I! The I length tIF is equal to so, and data input/output is only between RDM.
The data bus and its pins (of the chip) are effectively used only during these R and D periods, and are idle during the remaining periods. The present invention seeks to improve this point - so ib
An example of this is shown in FIG. In the culvert 5 diagram, chain line frame 10
shows an integrated circuit cage as in FIG. 1, in which two memory blocks 12 and 14 are accommodated in FIG.
If the integrated circuit element 210 (which may be configured on a separate semiconductor chip) is 64 KRAM, then the memory 12.1
4 is valley! It is 12KRAM. Element 10 has RAS.

CAS% WE% Dln%Doui Address h
~ Wiring or terminal bins for each Memory Pro are installed.

12.14 receives these signals, but RAS.

For the CAS, one of the professional signals is received by the inverter 16.1B, and for the Rikigogu 14, these signals are inverted and received by the inverter 16.1B. In this way, the active period M and the reset period R in the memories 12 and 14 are exactly reversed, allowing continuous input/output of the next data.

To explain this with reference to FIG. 4, RAS and CAS are inverted by inverters 16 and 18 and input to the memory processor 14 at 9RA8% CAS. At the falling edge of RAS%CAS, memory processor 12 (indicated by B1) - Address R
OW ADD and column address COL ADD
The import is done, followed by the professional.

BIRD is performed to output 12 read data.

- When RAS rises and enters the memory set period BIR, RAS falls to 0 and then C
AS falls. As a result, the row and column addresses of memory program 14 (indicated by 12) are captured.
Subsequently, the heave setting data is output (82RD).

The active period B2m and reset period 82g of Memory Pro, Ri14 are those of Memory Pro, Ri12 BIA%B
It is the opposite of IR, and data input/output is performed continuously.Furthermore, if two memory processors are formed in one semiconductor memory chip, address buffers etc. can be shared.

For example, there are two address buffers: y 77 K f:c row system and column system, and the row address buffer takes in the row address of memory program B1 and stores M.
Output T1h to M1, then immediately reset, then take in the row address of memory block B2. As is clear from the figure, there is sufficient time for the operation of checking K), and the row address buffer can be shared by the memory blocks 11 and B2. Of course, it is necessary to provide a switching circuit on the output side of this row address buffer to switch the output destination to the address decoder of memory block B1 or the address decoder of memory block B2.

First, there are 4 m for the column address buffer.

The specification and selection of Memory Pro, B1 and B2 are as follows.
CAS l7) H(/'(), L(CI-nte W Nu
There is no need to add one address signal line (for one pit). That is, when RAS and CAS are low, data BIRD of memory block B1 is output, and when these are high, data B2RD of memory block B2 is output.

Section 5 shows the configuration of the inverter 16. Ql is a degreen type load transistor, Qx is an enhancement type driver transistor, and these constitute an inverter 16, which receives RAS and outputs the inverted RAS. Although not shown, the inverter 18 is also similar.

(Effects of power generation and relaxation) As explained above, according to the present invention, the data input/output capacity of the memory can be increased by effectively utilizing the data bus system connected to external circuits. It also has the advantage of being able to save money.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the external tW1 connection relationship of the memory chip, Fig. 2a11 is a diagram explaining its operation, Fig. 3 is a diagram showing the embodiment of the present invention, Fig. 4 is a diagram illustrating its operation 1, The ms diagram is a circuit diagram of a part of Figure II3, and the 6th diagram is a circuit diagram showing a part of the internal structure of the element in Figure B1. In the drawing, 10 is a cage, 12 and 14 are memory blocks, h to A1 are addresses, Dln, s Dout* input/output data, WEfi convolution enable signal, RAS is a row address strobe, and CAS is a column address strobe.

Claims (1)

[Claims] Constructed as an integrated circuit, two memory blocks are housed in a semiconductor memory device, and addresses, input data, output data, and embedding signals given to the memory device from the outside are directly shared between both memory processors. The row address strobe RA8 and column address strobe CA8 signals are applied directly to the 10,000 memory block, and are applied to the other memory block via an inverter. 1. A semiconductor device characterized in that a memory block of the memory block is set in a reset period.